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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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474efecb65
Part of the intention during the definition of the RISC-V kernel image header was to lay the groundwork for a future merge with the ARM64 image header. One error during my original review was not noticing that the RISC-V header's "magic" field was at a different size and position than the ARM64's "magic" field. If the existing ARM64 Image header parsing code were to attempt to parse an existing RISC-V kernel image header format, it would see a magic number 0. This is undesirable, since it's our intention to align as closely as possible with the ARM64 header format. Another problem was that the original "res3" field was not being initialized correctly to zero. Address these issues by creating a 32-bit "magic2" field in the RISC-V header which matches the ARM64 "magic" field. RISC-V binaries will store "RSC\x05" in this field. The intention is that the use of the existing 64-bit "magic" field in the RISC-V header will be deprecated over time. Increment the minor version number of the file format to indicate this change, and update the documentation accordingly. Fix the assembler directives in head.S to ensure that reserved fields are properly zero-initialized. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Reported-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Cc: Atish Patra <atish.patra@wdc.com> Cc: Karsten Merker <merker@debian.org> Link: https://lore.kernel.org/linux-riscv/194c2f10c9806720623430dbf0cc59a965e50448.camel@wdc.com/T/#u Link: https://lore.kernel.org/linux-riscv/mhng-755b14c4-8f35-4079-a7ff-e421fd1b02bc@palmer-si-x1e/T/#t
66 lines
1.6 KiB
C
66 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_IMAGE_H
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#define __ASM_IMAGE_H
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#define RISCV_IMAGE_MAGIC "RISCV\0\0\0"
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#define RISCV_IMAGE_MAGIC2 "RSC\x05"
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#define RISCV_IMAGE_FLAG_BE_SHIFT 0
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#define RISCV_IMAGE_FLAG_BE_MASK 0x1
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#define RISCV_IMAGE_FLAG_LE 0
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#define RISCV_IMAGE_FLAG_BE 1
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#ifdef CONFIG_CPU_BIG_ENDIAN
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#error conversion of header fields to LE not yet implemented
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#else
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#define __HEAD_FLAG_BE RISCV_IMAGE_FLAG_LE
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#endif
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#define __HEAD_FLAG(field) (__HEAD_FLAG_##field << \
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RISCV_IMAGE_FLAG_##field##_SHIFT)
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#define __HEAD_FLAGS (__HEAD_FLAG(BE))
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#define RISCV_HEADER_VERSION_MAJOR 0
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#define RISCV_HEADER_VERSION_MINOR 2
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#define RISCV_HEADER_VERSION (RISCV_HEADER_VERSION_MAJOR << 16 | \
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RISCV_HEADER_VERSION_MINOR)
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#ifndef __ASSEMBLY__
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/**
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* struct riscv_image_header - riscv kernel image header
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* @code0: Executable code
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* @code1: Executable code
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* @text_offset: Image load offset (little endian)
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* @image_size: Effective Image size (little endian)
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* @flags: kernel flags (little endian)
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* @version: version
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* @res1: reserved
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* @res2: reserved
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* @magic: Magic number (RISC-V specific; deprecated)
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* @magic2: Magic number 2 (to match the ARM64 'magic' field pos)
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* @res4: reserved (will be used for PE COFF offset)
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*
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* The intention is for this header format to be shared between multiple
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* architectures to avoid a proliferation of image header formats.
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*/
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struct riscv_image_header {
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u32 code0;
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u32 code1;
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u64 text_offset;
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u64 image_size;
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u64 flags;
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u32 version;
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u32 res1;
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u64 res2;
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u64 magic;
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u32 magic2;
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u32 res4;
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_IMAGE_H */
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