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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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338 lines
8.5 KiB
C
338 lines
8.5 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
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*
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* Portions of this file are derived from the ipw3945 project.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* Intel Linux Wireless <ilw@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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*****************************************************************************/
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#ifndef __il_io_h__
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#define __il_io_h__
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#include <linux/io.h>
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#include "iwl-dev.h"
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#include "iwl-debug.h"
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static inline void _il_write8(struct il_priv *il, u32 ofs, u8 val)
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{
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iowrite8(val, il->hw_base + ofs);
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}
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#define il_write8(il, ofs, val) _il_write8(il, ofs, val)
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static inline void _il_wr(struct il_priv *il, u32 ofs, u32 val)
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{
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iowrite32(val, il->hw_base + ofs);
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}
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static inline u32 _il_rd(struct il_priv *il, u32 ofs)
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{
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return ioread32(il->hw_base + ofs);
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}
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#define IL_POLL_INTERVAL 10 /* microseconds */
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static inline int
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_il_poll_bit(struct il_priv *il, u32 addr,
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u32 bits, u32 mask, int timeout)
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{
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int t = 0;
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do {
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if ((_il_rd(il, addr) & mask) == (bits & mask))
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return t;
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udelay(IL_POLL_INTERVAL);
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t += IL_POLL_INTERVAL;
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} while (t < timeout);
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return -ETIMEDOUT;
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}
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static inline void _il_set_bit(struct il_priv *il, u32 reg, u32 mask)
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{
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_il_wr(il, reg, _il_rd(il, reg) | mask);
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}
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static inline void il_set_bit(struct il_priv *p, u32 r, u32 m)
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{
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unsigned long reg_flags;
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spin_lock_irqsave(&p->reg_lock, reg_flags);
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_il_set_bit(p, r, m);
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spin_unlock_irqrestore(&p->reg_lock, reg_flags);
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}
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static inline void
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_il_clear_bit(struct il_priv *il, u32 reg, u32 mask)
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{
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_il_wr(il, reg, _il_rd(il, reg) & ~mask);
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}
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static inline void il_clear_bit(struct il_priv *p, u32 r, u32 m)
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{
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unsigned long reg_flags;
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spin_lock_irqsave(&p->reg_lock, reg_flags);
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_il_clear_bit(p, r, m);
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spin_unlock_irqrestore(&p->reg_lock, reg_flags);
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}
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static inline int _il_grab_nic_access(struct il_priv *il)
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{
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int ret;
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u32 val;
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/* this bit wakes up the NIC */
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_il_set_bit(il, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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/*
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* These bits say the device is running, and should keep running for
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* at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
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* but they do not indicate that embedded SRAM is restored yet;
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* 3945 and 4965 have volatile SRAM, and must save/restore contents
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* to/from host DRAM when sleeping/waking for power-saving.
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* Each direction takes approximately 1/4 millisecond; with this
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* overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
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* series of register accesses are expected (e.g. reading Event Log),
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* to keep device from sleeping.
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*
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* CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
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* SRAM is okay/restored. We don't check that here because this call
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* is just for hardware register access; but GP1 MAC_SLEEP check is a
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* good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
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*
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*/
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ret = _il_poll_bit(il, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
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(CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
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CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
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if (ret < 0) {
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val = _il_rd(il, CSR_GP_CNTRL);
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IL_ERR(
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"MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val);
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_il_wr(il, CSR_RESET,
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CSR_RESET_REG_FLAG_FORCE_NMI);
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return -EIO;
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}
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return 0;
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}
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static inline void _il_release_nic_access(struct il_priv *il)
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{
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_il_clear_bit(il, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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}
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static inline u32 il_rd(struct il_priv *il, u32 reg)
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{
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u32 value;
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unsigned long reg_flags;
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spin_lock_irqsave(&il->reg_lock, reg_flags);
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_il_grab_nic_access(il);
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value = _il_rd(il, reg);
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_il_release_nic_access(il);
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spin_unlock_irqrestore(&il->reg_lock, reg_flags);
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return value;
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}
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static inline void
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il_wr(struct il_priv *il, u32 reg, u32 value)
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{
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unsigned long reg_flags;
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spin_lock_irqsave(&il->reg_lock, reg_flags);
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if (!_il_grab_nic_access(il)) {
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_il_wr(il, reg, value);
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_il_release_nic_access(il);
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}
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spin_unlock_irqrestore(&il->reg_lock, reg_flags);
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}
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static inline void il_write_reg_buf(struct il_priv *il,
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u32 reg, u32 len, u32 *values)
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{
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u32 count = sizeof(u32);
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if (il != NULL && values != NULL) {
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for (; 0 < len; len -= count, reg += count, values++)
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il_wr(il, reg, *values);
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}
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}
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static inline int il_poll_bit(struct il_priv *il, u32 addr,
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u32 mask, int timeout)
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{
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int t = 0;
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do {
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if ((il_rd(il, addr) & mask) == mask)
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return t;
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udelay(IL_POLL_INTERVAL);
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t += IL_POLL_INTERVAL;
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} while (t < timeout);
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return -ETIMEDOUT;
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}
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static inline u32 _il_rd_prph(struct il_priv *il, u32 reg)
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{
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_il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
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rmb();
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return _il_rd(il, HBUS_TARG_PRPH_RDAT);
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}
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static inline u32 il_rd_prph(struct il_priv *il, u32 reg)
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{
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unsigned long reg_flags;
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u32 val;
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spin_lock_irqsave(&il->reg_lock, reg_flags);
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_il_grab_nic_access(il);
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val = _il_rd_prph(il, reg);
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_il_release_nic_access(il);
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spin_unlock_irqrestore(&il->reg_lock, reg_flags);
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return val;
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}
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static inline void _il_wr_prph(struct il_priv *il,
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u32 addr, u32 val)
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{
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_il_wr(il, HBUS_TARG_PRPH_WADDR,
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((addr & 0x0000FFFF) | (3 << 24)));
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wmb();
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_il_wr(il, HBUS_TARG_PRPH_WDAT, val);
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}
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static inline void
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il_wr_prph(struct il_priv *il, u32 addr, u32 val)
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{
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unsigned long reg_flags;
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spin_lock_irqsave(&il->reg_lock, reg_flags);
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if (!_il_grab_nic_access(il)) {
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_il_wr_prph(il, addr, val);
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_il_release_nic_access(il);
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}
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spin_unlock_irqrestore(&il->reg_lock, reg_flags);
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}
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#define _il_set_bits_prph(il, reg, mask) \
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_il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask))
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static inline void
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il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
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{
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unsigned long reg_flags;
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spin_lock_irqsave(&il->reg_lock, reg_flags);
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_il_grab_nic_access(il);
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_il_set_bits_prph(il, reg, mask);
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_il_release_nic_access(il);
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spin_unlock_irqrestore(&il->reg_lock, reg_flags);
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}
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#define _il_set_bits_mask_prph(il, reg, bits, mask) \
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_il_wr_prph(il, reg, \
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((_il_rd_prph(il, reg) & mask) | bits))
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static inline void il_set_bits_mask_prph(struct il_priv *il, u32 reg,
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u32 bits, u32 mask)
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{
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unsigned long reg_flags;
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spin_lock_irqsave(&il->reg_lock, reg_flags);
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_il_grab_nic_access(il);
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_il_set_bits_mask_prph(il, reg, bits, mask);
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_il_release_nic_access(il);
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spin_unlock_irqrestore(&il->reg_lock, reg_flags);
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}
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static inline void il_clear_bits_prph(struct il_priv
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*il, u32 reg, u32 mask)
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{
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unsigned long reg_flags;
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u32 val;
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spin_lock_irqsave(&il->reg_lock, reg_flags);
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_il_grab_nic_access(il);
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val = _il_rd_prph(il, reg);
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_il_wr_prph(il, reg, (val & ~mask));
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_il_release_nic_access(il);
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spin_unlock_irqrestore(&il->reg_lock, reg_flags);
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}
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static inline u32 il_read_targ_mem(struct il_priv *il, u32 addr)
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{
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unsigned long reg_flags;
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u32 value;
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spin_lock_irqsave(&il->reg_lock, reg_flags);
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_il_grab_nic_access(il);
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_il_wr(il, HBUS_TARG_MEM_RADDR, addr);
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rmb();
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value = _il_rd(il, HBUS_TARG_MEM_RDAT);
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_il_release_nic_access(il);
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spin_unlock_irqrestore(&il->reg_lock, reg_flags);
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return value;
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}
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static inline void
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il_write_targ_mem(struct il_priv *il, u32 addr, u32 val)
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{
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unsigned long reg_flags;
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spin_lock_irqsave(&il->reg_lock, reg_flags);
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if (!_il_grab_nic_access(il)) {
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_il_wr(il, HBUS_TARG_MEM_WADDR, addr);
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wmb();
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_il_wr(il, HBUS_TARG_MEM_WDAT, val);
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_il_release_nic_access(il);
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}
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spin_unlock_irqrestore(&il->reg_lock, reg_flags);
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}
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static inline void
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il_write_targ_mem_buf(struct il_priv *il, u32 addr,
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u32 len, u32 *values)
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{
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unsigned long reg_flags;
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spin_lock_irqsave(&il->reg_lock, reg_flags);
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if (!_il_grab_nic_access(il)) {
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_il_wr(il, HBUS_TARG_MEM_WADDR, addr);
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wmb();
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for (; 0 < len; len -= sizeof(u32), values++)
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_il_wr(il,
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HBUS_TARG_MEM_WDAT, *values);
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_il_release_nic_access(il);
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}
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spin_unlock_irqrestore(&il->reg_lock, reg_flags);
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}
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#endif
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