mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 19:21:17 +07:00
8d27e08191
Clean up some of the subtype IRQ definitions for IPR IRQ, and consolidate the make_ipr_irq() definitions by dropping maskpos. SH-4A was the only thing interested in the maskpos, and this should be handled through INTC2 rather than IPR. Signed-off-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
327 lines
7.4 KiB
C
327 lines
7.4 KiB
C
#ifndef __ASM_SH_IRQ_SH7780_H
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#define __ASM_SH_IRQ_SH7780_H
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/*
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* linux/include/asm-sh/irq-sh7780.h
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*
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* Copyright (C) 2004 Takashi SHUDO <shudo@hitachi-ul.co.jp>
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*/
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#ifdef CONFIG_IDE
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# ifndef IRQ_CFCARD
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# define IRQ_CFCARD 14
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# endif
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# ifndef IRQ_PCMCIA
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# define IRQ_PCMCIA 15
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# endif
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#endif
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#define INTC_BASE 0xffd00000
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#define INTC_ICR0 (INTC_BASE+0x0)
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#define INTC_ICR1 (INTC_BASE+0x1c)
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#define INTC_INTPRI (INTC_BASE+0x10)
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#define INTC_INTREQ (INTC_BASE+0x24)
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#define INTC_INTMSK0 (INTC_BASE+0x44)
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#define INTC_INTMSK1 (INTC_BASE+0x48)
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#define INTC_INTMSK2 (INTC_BASE+0x40080)
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#define INTC_INTMSKCLR0 (INTC_BASE+0x64)
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#define INTC_INTMSKCLR1 (INTC_BASE+0x68)
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#define INTC_INTMSKCLR2 (INTC_BASE+0x40084)
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#define INTC_NMIFCR (INTC_BASE+0xc0)
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#define INTC_USERIMASK (INTC_BASE+0x30000)
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#define INTC_INT2PRI0 (INTC_BASE+0x40000)
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#define INTC_INT2PRI1 (INTC_BASE+0x40004)
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#define INTC_INT2PRI2 (INTC_BASE+0x40008)
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#define INTC_INT2PRI3 (INTC_BASE+0x4000c)
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#define INTC_INT2PRI4 (INTC_BASE+0x40010)
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#define INTC_INT2PRI5 (INTC_BASE+0x40014)
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#define INTC_INT2PRI6 (INTC_BASE+0x40018)
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#define INTC_INT2PRI7 (INTC_BASE+0x4001c)
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#define INTC_INT2A0 (INTC_BASE+0x40030)
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#define INTC_INT2A1 (INTC_BASE+0x40034)
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#define INTC_INT2MSKR (INTC_BASE+0x40038)
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#define INTC_INT2MSKCR (INTC_BASE+0x4003c)
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#define INTC_INT2B0 (INTC_BASE+0x40040)
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#define INTC_INT2B1 (INTC_BASE+0x40044)
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#define INTC_INT2B2 (INTC_BASE+0x40048)
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#define INTC_INT2B3 (INTC_BASE+0x4004c)
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#define INTC_INT2B4 (INTC_BASE+0x40050)
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#define INTC_INT2B5 (INTC_BASE+0x40054)
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#define INTC_INT2B6 (INTC_BASE+0x40058)
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#define INTC_INT2B7 (INTC_BASE+0x4005c)
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#define INTC_INT2GPIC (INTC_BASE+0x40090)
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/*
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NOTE:
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*_IRQ = (INTEVT2 - 0x200)/0x20
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*/
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/* IRQ 0-7 line external int*/
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#define IRQ0_IRQ 2
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#define IRQ0_IPR_ADDR INTC_INTPRI
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#define IRQ0_IPR_POS 7
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#define IRQ0_PRIORITY 2
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#define IRQ1_IRQ 4
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#define IRQ1_IPR_ADDR INTC_INTPRI
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#define IRQ1_IPR_POS 6
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#define IRQ1_PRIORITY 2
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#define IRQ2_IRQ 6
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#define IRQ2_IPR_ADDR INTC_INTPRI
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#define IRQ2_IPR_POS 5
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#define IRQ2_PRIORITY 2
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#define IRQ3_IRQ 8
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#define IRQ3_IPR_ADDR INTC_INTPRI
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#define IRQ3_IPR_POS 4
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#define IRQ3_PRIORITY 2
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#define IRQ4_IRQ 10
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#define IRQ4_IPR_ADDR INTC_INTPRI
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#define IRQ4_IPR_POS 3
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#define IRQ4_PRIORITY 2
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#define IRQ5_IRQ 12
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#define IRQ5_IPR_ADDR INTC_INTPRI
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#define IRQ5_IPR_POS 2
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#define IRQ5_PRIORITY 2
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#define IRQ6_IRQ 14
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#define IRQ6_IPR_ADDR INTC_INTPRI
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#define IRQ6_IPR_POS 1
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#define IRQ6_PRIORITY 2
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#define IRQ7_IRQ 0
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#define IRQ7_IPR_ADDR INTC_INTPRI
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#define IRQ7_IPR_POS 0
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#define IRQ7_PRIORITY 2
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/* TMU */
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/* ch0 */
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#define TMU_IRQ 28
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#define TMU_IPR_ADDR INTC_INT2PRI0
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#define TMU_IPR_POS 3
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#define TMU_PRIORITY 2
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#define TIMER_IRQ 28
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#define TIMER_IPR_ADDR INTC_INT2PRI0
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#define TIMER_IPR_POS 3
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#define TIMER_PRIORITY 2
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/* ch 1*/
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#define TMU_CH1_IRQ 29
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#define TMU_CH1_IPR_ADDR INTC_INT2PRI0
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#define TMU_CH1_IPR_POS 2
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#define TMU_CH1_PRIORITY 2
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#define TIMER1_IRQ 29
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#define TIMER1_IPR_ADDR INTC_INT2PRI0
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#define TIMER1_IPR_POS 2
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#define TIMER1_PRIORITY 2
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/* ch 2*/
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#define TMU_CH2_IRQ 30
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#define TMU_CH2_IPR_ADDR INTC_INT2PRI0
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#define TMU_CH2_IPR_POS 1
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#define TMU_CH2_PRIORITY 2
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/* ch 2 Input capture */
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#define TMU_CH2IC_IRQ 31
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#define TMU_CH2IC_IPR_ADDR INTC_INT2PRI0
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#define TMU_CH2IC_IPR_POS 0
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#define TMU_CH2IC_PRIORITY 2
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/* ch 3 */
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#define TMU_CH3_IRQ 96
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#define TMU_CH3_IPR_ADDR INTC_INT2PRI1
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#define TMU_CH3_IPR_POS 3
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#define TMU_CH3_PRIORITY 2
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/* ch 4 */
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#define TMU_CH4_IRQ 97
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#define TMU_CH4_IPR_ADDR INTC_INT2PRI1
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#define TMU_CH4_IPR_POS 2
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#define TMU_CH4_PRIORITY 2
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/* ch 5*/
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#define TMU_CH5_IRQ 98
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#define TMU_CH5_IPR_ADDR INTC_INT2PRI1
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#define TMU_CH5_IPR_POS 1
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#define TMU_CH5_PRIORITY 2
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#define RTC_IRQ 22
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#define RTC_IPR_ADDR INTC_INT2PRI1
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#define RTC_IPR_POS 0
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#define RTC_PRIORITY TIMER_PRIORITY
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/* SCIF0 */
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#define SCIF0_ERI_IRQ 40
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#define SCIF0_RXI_IRQ 41
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#define SCIF0_BRI_IRQ 42
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#define SCIF0_TXI_IRQ 43
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#define SCIF0_IPR_ADDR INTC_INT2PRI2
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#define SCIF0_IPR_POS 3
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#define SCIF0_PRIORITY 3
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/* SCIF1 */
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#define SCIF1_ERI_IRQ 76
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#define SCIF1_RXI_IRQ 77
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#define SCIF1_BRI_IRQ 78
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#define SCIF1_TXI_IRQ 79
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#define SCIF1_IPR_ADDR INTC_INT2PRI2
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#define SCIF1_IPR_POS 2
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#define SCIF1_PRIORITY 3
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#define WDT_IRQ 27
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#define WDT_IPR_ADDR INTC_INT2PRI2
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#define WDT_IPR_POS 1
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#define WDT_PRIORITY 2
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/* DMAC(0) */
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#define DMINT0_IRQ 34
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#define DMINT1_IRQ 35
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#define DMINT2_IRQ 36
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#define DMINT3_IRQ 37
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#define DMINT4_IRQ 44
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#define DMINT5_IRQ 45
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#define DMINT6_IRQ 46
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#define DMINT7_IRQ 47
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#define DMAE_IRQ 38
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#define DMA0_IPR_ADDR INTC_INT2PRI3
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#define DMA0_IPR_POS 2
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#define DMA0_PRIORITY 7
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/* DMAC(1) */
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#define DMINT8_IRQ 92
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#define DMINT9_IRQ 93
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#define DMINT10_IRQ 94
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#define DMINT11_IRQ 95
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#define DMA1_IPR_ADDR INTC_INT2PRI3
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#define DMA1_IPR_POS 1
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#define DMA1_PRIORITY 7
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#define DMTE0_IRQ DMINT0_IRQ
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#define DMTE4_IRQ DMINT4_IRQ
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#define DMA_IPR_ADDR DMA0_IPR_ADDR
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#define DMA_IPR_POS DMA0_IPR_POS
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#define DMA_PRIORITY DMA0_PRIORITY
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/* CMT */
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#define CMT_IRQ 56
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#define CMT_IPR_ADDR INTC_INT2PRI4
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#define CMT_IPR_POS 3
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#define CMT_PRIORITY 0
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/* HAC */
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#define HAC_IRQ 60
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#define HAC_IPR_ADDR INTC_INT2PRI4
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#define HAC_IPR_POS 2
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#define CMT_PRIORITY 0
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/* PCIC(0) */
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#define PCIC0_IRQ 64
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#define PCIC0_IPR_ADDR INTC_INT2PRI4
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#define PCIC0_IPR_POS 1
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#define PCIC0_PRIORITY 2
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/* PCIC(1) */
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#define PCIC1_IRQ 65
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#define PCIC1_IPR_ADDR INTC_INT2PRI4
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#define PCIC1_IPR_POS 0
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#define PCIC1_PRIORITY 2
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/* PCIC(2) */
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#define PCIC2_IRQ 66
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#define PCIC2_IPR_ADDR INTC_INT2PRI5
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#define PCIC2_IPR_POS 3
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#define PCIC2_PRIORITY 2
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/* PCIC(3) */
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#define PCIC3_IRQ 67
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#define PCIC3_IPR_ADDR INTC_INT2PRI5
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#define PCIC3_IPR_POS 2
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#define PCIC3_PRIORITY 2
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/* PCIC(4) */
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#define PCIC4_IRQ 68
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#define PCIC4_IPR_ADDR INTC_INT2PRI5
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#define PCIC4_IPR_POS 1
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#define PCIC4_PRIORITY 2
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/* PCIC(5) */
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#define PCICERR_IRQ 69
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#define PCICPWD3_IRQ 70
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#define PCICPWD2_IRQ 71
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#define PCICPWD1_IRQ 72
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#define PCICPWD0_IRQ 73
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#define PCIC5_IPR_ADDR INTC_INT2PRI5
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#define PCIC5_IPR_POS 0
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#define PCIC5_PRIORITY 2
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/* SIOF */
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#define SIOF_IRQ 80
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#define SIOF_IPR_ADDR INTC_INT2PRI6
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#define SIOF_IPR_POS 3
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#define SIOF_PRIORITY 3
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/* HSPI */
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#define HSPI_IRQ 84
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#define HSPI_IPR_ADDR INTC_INT2PRI6
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#define HSPI_IPR_POS 2
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#define HSPI_PRIORITY 3
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/* MMCIF */
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#define MMCIF_FSTAT_IRQ 88
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#define MMCIF_TRAN_IRQ 89
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#define MMCIF_ERR_IRQ 90
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#define MMCIF_FRDY_IRQ 91
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#define MMCIF_IPR_ADDR INTC_INT2PRI6
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#define MMCIF_IPR_POS 1
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#define HSPI_PRIORITY 3
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/* SSI */
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#define SSI_IRQ 100
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#define SSI_IPR_ADDR INTC_INT2PRI6
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#define SSI_IPR_POS 0
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#define SSI_PRIORITY 3
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/* FLCTL */
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#define FLCTL_FLSTE_IRQ 104
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#define FLCTL_FLTEND_IRQ 105
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#define FLCTL_FLTRQ0_IRQ 106
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#define FLCTL_FLTRQ1_IRQ 107
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#define FLCTL_IPR_ADDR INTC_INT2PRI7
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#define FLCTL_IPR_POS 3
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#define FLCTL_PRIORITY 3
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/* GPIO */
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#define GPIO0_IRQ 108
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#define GPIO1_IRQ 109
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#define GPIO2_IRQ 110
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#define GPIO3_IRQ 111
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#define GPIO_IPR_ADDR INTC_INT2PRI7
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#define GPIO_IPR_POS 2
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#define GPIO_PRIORITY 3
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#define INTC_TMU0_MSK 0
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#define INTC_TMU3_MSK 1
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#define INTC_RTC_MSK 2
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#define INTC_SCIF0_MSK 3
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#define INTC_SCIF1_MSK 4
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#define INTC_WDT_MSK 5
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#define INTC_HUID_MSK 7
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#define INTC_DMAC0_MSK 8
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#define INTC_DMAC1_MSK 9
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#define INTC_CMT_MSK 12
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#define INTC_HAC_MSK 13
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#define INTC_PCIC0_MSK 14
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#define INTC_PCIC1_MSK 15
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#define INTC_PCIC2_MSK 16
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#define INTC_PCIC3_MSK 17
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#define INTC_PCIC4_MSK 18
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#define INTC_PCIC5_MSK 19
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#define INTC_SIOF_MSK 20
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#define INTC_HSPI_MSK 21
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#define INTC_MMCIF_MSK 22
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#define INTC_SSI_MSK 23
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#define INTC_FLCTL_MSK 24
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#define INTC_GPIO_MSK 25
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#endif /* __ASM_SH_IRQ_SH7780_H */
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