mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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13da9e200f
This reverts commitb3b77c8cae, which was also totally broken (see commit0d2daf5cc8that reverted the crc32 version of it). As reported by Stephen Rothwell, it causes problems on big-endian machines: > In file included from fs/jfs/jfs_types.h:33, > from fs/jfs/jfs_incore.h:26, > from fs/jfs/file.c:22: > fs/jfs/endian24.h:36:101: warning: "__LITTLE_ENDIAN" is not defined The kernel has never had that crazy "__BYTE_ORDER == __LITTLE_ENDIAN" model. It's not how we do things, and it isn't how we _should_ do things. So don't go there. Requested-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
121 lines
4.1 KiB
C
121 lines
4.1 KiB
C
/*
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* arch/sparc64/math-emu/sfp-util.h
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*
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* Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
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* Copyright (C) 1999 David S. Miller (davem@redhat.com)
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*
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <asm/byteorder.h>
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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__asm__ ("addcc %4,%5,%1\n\t" \
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"add %2,%3,%0\n\t" \
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"bcs,a,pn %%xcc, 1f\n\t" \
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"add %0, 1, %0\n" \
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"1:" \
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: "=r" ((UDItype)(sh)), \
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"=&r" ((UDItype)(sl)) \
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: "r" ((UDItype)(ah)), \
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"r" ((UDItype)(bh)), \
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"r" ((UDItype)(al)), \
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"r" ((UDItype)(bl)) \
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: "cc")
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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__asm__ ("subcc %4,%5,%1\n\t" \
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"sub %2,%3,%0\n\t" \
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"bcs,a,pn %%xcc, 1f\n\t" \
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"sub %0, 1, %0\n" \
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"1:" \
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: "=r" ((UDItype)(sh)), \
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"=&r" ((UDItype)(sl)) \
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: "r" ((UDItype)(ah)), \
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"r" ((UDItype)(bh)), \
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"r" ((UDItype)(al)), \
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"r" ((UDItype)(bl)) \
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: "cc")
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#define umul_ppmm(wh, wl, u, v) \
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do { \
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UDItype tmp1, tmp2, tmp3, tmp4; \
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__asm__ __volatile__ ( \
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"srl %7,0,%3\n\t" \
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"mulx %3,%6,%1\n\t" \
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"srlx %6,32,%2\n\t" \
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"mulx %2,%3,%4\n\t" \
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"sllx %4,32,%5\n\t" \
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"srl %6,0,%3\n\t" \
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"sub %1,%5,%5\n\t" \
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"srlx %5,32,%5\n\t" \
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"addcc %4,%5,%4\n\t" \
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"srlx %7,32,%5\n\t" \
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"mulx %3,%5,%3\n\t" \
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"mulx %2,%5,%5\n\t" \
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"sethi %%hi(0x80000000),%2\n\t" \
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"addcc %4,%3,%4\n\t" \
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"srlx %4,32,%4\n\t" \
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"add %2,%2,%2\n\t" \
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"movcc %%xcc,%%g0,%2\n\t" \
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"addcc %5,%4,%5\n\t" \
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"sllx %3,32,%3\n\t" \
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"add %1,%3,%1\n\t" \
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"add %5,%2,%0" \
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: "=r" ((UDItype)(wh)), \
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"=&r" ((UDItype)(wl)), \
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"=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
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: "r" ((UDItype)(u)), \
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"r" ((UDItype)(v)) \
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: "cc"); \
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} while (0)
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#define udiv_qrnnd(q, r, n1, n0, d) \
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do { \
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UWtype __d1, __d0, __q1, __q0, __r1, __r0, __m; \
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__d1 = (d >> 32); \
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__d0 = (USItype)d; \
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\
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__r1 = (n1) % __d1; \
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__q1 = (n1) / __d1; \
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__m = (UWtype) __q1 * __d0; \
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__r1 = (__r1 << 32) | (n0 >> 32); \
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if (__r1 < __m) \
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{ \
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__q1--, __r1 += (d); \
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if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */ \
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if (__r1 < __m) \
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__q1--, __r1 += (d); \
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} \
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__r1 -= __m; \
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\
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__r0 = __r1 % __d1; \
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__q0 = __r1 / __d1; \
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__m = (UWtype) __q0 * __d0; \
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__r0 = (__r0 << 32) | ((USItype)n0); \
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if (__r0 < __m) \
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{ \
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__q0--, __r0 += (d); \
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if (__r0 >= (d)) \
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if (__r0 < __m) \
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__q0--, __r0 += (d); \
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} \
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__r0 -= __m; \
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\
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(q) = (UWtype) (__q1 << 32) | __q0; \
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(r) = __r0; \
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} while (0)
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#define UDIV_NEEDS_NORMALIZATION 1
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#define abort() \
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return 0
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#ifdef __BIG_ENDIAN
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#define __BYTE_ORDER __BIG_ENDIAN
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#else
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#define __BYTE_ORDER __LITTLE_ENDIAN
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#endif
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