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4603f53a1d
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
are flagged as __cpuinit -- so if we remove the __cpuinit from
arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
content into no-ops as early as possible, since that will get rid
of these warnings. In any case, they are temporary and harmless.
This removes all the arch/sh uses of the __cpuinit macros from
all C files. Currently sh does not have any __CPUINIT used in
assembly files.
[1] https://lkml.org/lkml/2013/5/20/589
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: linux-sh@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
76 lines
2.2 KiB
C
76 lines
2.2 KiB
C
/*
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* arch/sh/kernel/cpu/sh5/probe.c
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*
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* CPU Subtype Probing for SH-5.
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*
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* Copyright (C) 2000, 2001 Paolo Alberelli
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* Copyright (C) 2003 - 2007 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/string.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/tlb.h>
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void cpu_probe(void)
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{
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unsigned long long cir;
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/*
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* Do peeks in real mode to avoid having to set up a mapping for
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* the WPC registers. On SH5-101 cut2, such a mapping would be
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* exposed to an address translation erratum which would make it
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* hard to set up correctly.
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*/
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cir = peek_real_address_q(0x0d000008);
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if ((cir & 0xffff) == 0x5103)
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boot_cpu_data.type = CPU_SH5_103;
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else if (((cir >> 32) & 0xffff) == 0x51e2)
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/* CPU.VCR aliased at CIR address on SH5-101 */
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boot_cpu_data.type = CPU_SH5_101;
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boot_cpu_data.family = CPU_FAMILY_SH5;
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/*
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* First, setup some sane values for the I-cache.
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*/
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boot_cpu_data.icache.ways = 4;
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boot_cpu_data.icache.sets = 256;
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boot_cpu_data.icache.linesz = L1_CACHE_BYTES;
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boot_cpu_data.icache.way_incr = (1 << 13);
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boot_cpu_data.icache.entry_shift = 5;
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boot_cpu_data.icache.way_size = boot_cpu_data.icache.sets *
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boot_cpu_data.icache.linesz;
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boot_cpu_data.icache.entry_mask = 0x1fe0;
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boot_cpu_data.icache.flags = 0;
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/*
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* Next, setup some sane values for the D-cache.
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*
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* On the SH5, these are pretty consistent with the I-cache settings,
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* so we just copy over the existing definitions.. these can be fixed
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* up later, especially if we add runtime CPU probing.
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*
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* Though in the meantime it saves us from having to duplicate all of
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* the above definitions..
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*/
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boot_cpu_data.dcache = boot_cpu_data.icache;
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/*
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* Setup any cache-related flags here
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*/
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#if defined(CONFIG_CACHE_WRITETHROUGH)
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set_bit(SH_CACHE_MODE_WT, &(boot_cpu_data.dcache.flags));
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#elif defined(CONFIG_CACHE_WRITEBACK)
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set_bit(SH_CACHE_MODE_WB, &(boot_cpu_data.dcache.flags));
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#endif
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/* Setup some I/D TLB defaults */
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sh64_tlb_init();
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}
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