mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-07 22:36:39 +07:00
61af4d8dce
The module 0 style clocks, or storage module clocks as named in the official SDK, are almost the same as the module 0 clocks on earlier Allwinner SoCs. The only difference is wider mux register bits. As with earlier Allwinner SoCs, mmc module clocks are a special case of mod0 clocks, with phase controls for 2 child clocks, output and sample. This patch adds support for both. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
||
---|---|---|
.. | ||
clk-a10-hosc.c | ||
clk-a20-gmac.c | ||
clk-factors.c | ||
clk-factors.h | ||
clk-mod0.c | ||
clk-sun6i-apb0-gates.c | ||
clk-sun6i-apb0.c | ||
clk-sun6i-ar100.c | ||
clk-sun8i-apb0.c | ||
clk-sun8i-mbus.c | ||
clk-sun9i-core.c | ||
clk-sunxi.c | ||
Makefile |