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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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43651b15de
Add information to the shared APMU code regarding the APMU instance used to control the CA7 cores. This can be used on r8a7790 and r8a73a4, but should most likely be converted to DT in the future. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
196 lines
4.1 KiB
C
196 lines
4.1 KiB
C
/*
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* SMP support for SoCs with APMU
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*
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/of_address.h>
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#include <linux/smp.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#include <asm/smp_plat.h>
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#include <mach/common.h>
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static struct {
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void __iomem *iomem;
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int bit;
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} apmu_cpus[CONFIG_NR_CPUS];
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#define WUPCR_OFFS 0x10
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#define PSTR_OFFS 0x40
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#define CPUNCR_OFFS(n) (0x100 + (0x10 * (n)))
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static int apmu_power_on(void __iomem *p, int bit)
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{
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/* request power on */
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writel_relaxed(BIT(bit), p + WUPCR_OFFS);
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/* wait for APMU to finish */
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while (readl_relaxed(p + WUPCR_OFFS) != 0)
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;
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return 0;
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}
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static int apmu_power_off(void __iomem *p, int bit)
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{
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/* request Core Standby for next WFI */
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writel_relaxed(3, p + CPUNCR_OFFS(bit));
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return 0;
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}
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static int apmu_power_off_poll(void __iomem *p, int bit)
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{
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int k;
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for (k = 0; k < 1000; k++) {
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if (((readl_relaxed(p + PSTR_OFFS) >> (bit * 4)) & 0x03) == 3)
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return 1;
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mdelay(1);
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}
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return 0;
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}
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static int apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu))
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{
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void __iomem *p = apmu_cpus[cpu].iomem;
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return p ? fn(p, apmu_cpus[cpu].bit) : -EINVAL;
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}
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static void apmu_init_cpu(struct resource *res, int cpu, int bit)
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{
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if (apmu_cpus[cpu].iomem)
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return;
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apmu_cpus[cpu].iomem = ioremap_nocache(res->start, resource_size(res));
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apmu_cpus[cpu].bit = bit;
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pr_debug("apmu ioremap %d %d 0x%08x 0x%08x\n", cpu, bit,
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res->start, resource_size(res));
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}
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static struct {
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struct resource iomem;
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int cpus[4];
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} apmu_config[] = {
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{
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.iomem = DEFINE_RES_MEM(0xe6152000, 0x88),
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.cpus = { 0, 1, 2, 3 },
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},
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{
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.iomem = DEFINE_RES_MEM(0xe6151000, 0x88),
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.cpus = { 0x100, 0x101, 0x102, 0x103 },
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}
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};
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static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit))
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{
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u32 id;
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int k;
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int bit, index;
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bool is_allowed;
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for (k = 0; k < ARRAY_SIZE(apmu_config); k++) {
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/* only enable the cluster that includes the boot CPU */
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is_allowed = false;
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for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) {
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id = apmu_config[k].cpus[bit];
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if (id >= 0) {
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if (id == cpu_logical_map(0))
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is_allowed = true;
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}
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}
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if (!is_allowed)
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continue;
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for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) {
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id = apmu_config[k].cpus[bit];
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if (id >= 0) {
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index = get_logical_index(id);
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if (index >= 0)
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fn(&apmu_config[k].iomem, index, bit);
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}
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}
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}
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}
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void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus)
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{
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/* install boot code shared by all CPUs */
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shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
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shmobile_boot_arg = MPIDR_HWID_BITMASK;
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/* perform per-cpu setup */
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apmu_parse_cfg(apmu_init_cpu);
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}
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int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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/* For this particular CPU register boot vector */
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shmobile_smp_hook(cpu, virt_to_phys(shmobile_invalidate_start), 0);
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return apmu_wrap(cpu, apmu_power_on);
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}
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#ifdef CONFIG_HOTPLUG_CPU
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/* nicked from arch/arm/mach-exynos/hotplug.c */
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static inline void cpu_enter_lowpower_a15(void)
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{
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unsigned int v;
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asm volatile(
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" mrc p15, 0, %0, c1, c0, 0\n"
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" bic %0, %0, %1\n"
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" mcr p15, 0, %0, c1, c0, 0\n"
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: "=&r" (v)
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: "Ir" (CR_C)
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: "cc");
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flush_cache_louis();
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asm volatile(
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/*
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* Turn off coherency
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*/
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" mrc p15, 0, %0, c1, c0, 1\n"
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" bic %0, %0, %1\n"
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" mcr p15, 0, %0, c1, c0, 1\n"
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: "=&r" (v)
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: "Ir" (0x40)
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: "cc");
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isb();
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dsb();
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}
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void shmobile_smp_apmu_cpu_die(unsigned int cpu)
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{
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/* For this particular CPU deregister boot vector */
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shmobile_smp_hook(cpu, 0, 0);
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/* Select next sleep mode using the APMU */
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apmu_wrap(cpu, apmu_power_off);
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/* Do ARM specific CPU shutdown */
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cpu_enter_lowpower_a15();
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/* jump to shared mach-shmobile sleep / reset code */
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shmobile_smp_sleep();
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}
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int shmobile_smp_apmu_cpu_kill(unsigned int cpu)
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{
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return apmu_wrap(cpu, apmu_power_off_poll);
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}
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#endif
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