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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
6173269038
Add Kconfig, PCI ID and chip info for EHL platform. Note that the core mask is different from previous platforms, only Core0 can be controlled by the host. Additional patches will be required for multi-core functionality. Signed-off-by: Pan Xiuli <xiuli.pan@linux.intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20190815155749.29304-5-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
330 lines
8.7 KiB
C
330 lines
8.7 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2018 Intel Corporation. All rights reserved.
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//
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// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
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// Rander Wang <rander.wang@intel.com>
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// Keyon Jie <yang.jie@linux.intel.com>
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//
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/*
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* Hardware interface for audio DSP on Cannonlake.
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*/
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#include "../ops.h"
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#include "hda.h"
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static const struct snd_sof_debugfs_map cnl_dsp_debugfs[] = {
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{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
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{"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
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{"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
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};
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static void cnl_ipc_host_done(struct snd_sof_dev *sdev);
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static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev);
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static irqreturn_t cnl_ipc_irq_thread(int irq, void *context)
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{
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struct snd_sof_dev *sdev = context;
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u32 hipci;
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u32 hipcida;
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u32 hipctdr;
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u32 hipctdd;
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u32 msg;
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u32 msg_ext;
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bool ipc_irq = false;
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hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
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hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
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hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDD);
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hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR);
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/* reply message from DSP */
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if (hipcida & CNL_DSP_REG_HIPCIDA_DONE) {
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msg_ext = hipci & CNL_DSP_REG_HIPCIDR_MSG_MASK;
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msg = hipcida & CNL_DSP_REG_HIPCIDA_MSG_MASK;
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dev_vdbg(sdev->dev,
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"ipc: firmware response, msg:0x%x, msg_ext:0x%x\n",
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msg, msg_ext);
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/* mask Done interrupt */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
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CNL_DSP_REG_HIPCCTL,
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CNL_DSP_REG_HIPCCTL_DONE, 0);
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spin_lock_irq(&sdev->ipc_lock);
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/* handle immediate reply from DSP core */
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hda_dsp_ipc_get_reply(sdev);
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snd_sof_ipc_reply(sdev, msg);
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if (sdev->code_loading) {
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sdev->code_loading = 0;
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wake_up(&sdev->waitq);
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}
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cnl_ipc_dsp_done(sdev);
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spin_unlock_irq(&sdev->ipc_lock);
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ipc_irq = true;
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}
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/* new message from DSP */
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if (hipctdr & CNL_DSP_REG_HIPCTDR_BUSY) {
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msg = hipctdr & CNL_DSP_REG_HIPCTDR_MSG_MASK;
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msg_ext = hipctdd & CNL_DSP_REG_HIPCTDD_MSG_MASK;
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dev_vdbg(sdev->dev,
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"ipc: firmware initiated, msg:0x%x, msg_ext:0x%x\n",
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msg, msg_ext);
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/* handle messages from DSP */
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if ((hipctdr & SOF_IPC_PANIC_MAGIC_MASK) ==
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SOF_IPC_PANIC_MAGIC) {
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snd_sof_dsp_panic(sdev, HDA_DSP_PANIC_OFFSET(msg_ext));
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} else {
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snd_sof_ipc_msgs_rx(sdev);
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}
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cnl_ipc_host_done(sdev);
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ipc_irq = true;
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}
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if (!ipc_irq) {
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/*
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* This interrupt is not shared so no need to return IRQ_NONE.
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*/
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dev_dbg_ratelimited(sdev->dev,
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"nothing to do in IPC IRQ thread\n");
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}
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/* re-enable IPC interrupt */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
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HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
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return IRQ_HANDLED;
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}
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static void cnl_ipc_host_done(struct snd_sof_dev *sdev)
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{
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/*
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* clear busy interrupt to tell dsp controller this
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* interrupt has been accepted, not trigger it again
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*/
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snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
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CNL_DSP_REG_HIPCTDR,
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CNL_DSP_REG_HIPCTDR_BUSY,
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CNL_DSP_REG_HIPCTDR_BUSY);
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/*
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* set done bit to ack dsp the msg has been
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* processed and send reply msg to dsp
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*/
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snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
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CNL_DSP_REG_HIPCTDA,
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CNL_DSP_REG_HIPCTDA_DONE,
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CNL_DSP_REG_HIPCTDA_DONE);
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}
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static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev)
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{
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/*
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* set DONE bit - tell DSP we have received the reply msg
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* from DSP, and processed it, don't send more reply to host
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*/
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snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
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CNL_DSP_REG_HIPCIDA,
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CNL_DSP_REG_HIPCIDA_DONE,
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CNL_DSP_REG_HIPCIDA_DONE);
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/* unmask Done interrupt */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
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CNL_DSP_REG_HIPCCTL,
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CNL_DSP_REG_HIPCCTL_DONE,
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CNL_DSP_REG_HIPCCTL_DONE);
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}
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static int cnl_ipc_send_msg(struct snd_sof_dev *sdev,
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struct snd_sof_ipc_msg *msg)
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{
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/* send the message */
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sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
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msg->msg_size);
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snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
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CNL_DSP_REG_HIPCIDR_BUSY);
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return 0;
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}
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static void cnl_ipc_dump(struct snd_sof_dev *sdev)
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{
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u32 hipcctl;
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u32 hipcida;
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u32 hipctdr;
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hda_ipc_irq_dump(sdev);
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/* read IPC status */
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hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
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hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCCTL);
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hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
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/* dump the IPC regs */
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/* TODO: parse the raw msg */
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dev_err(sdev->dev,
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"error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
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hipcida, hipctdr, hipcctl);
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}
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/* cannonlake ops */
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const struct snd_sof_dsp_ops sof_cnl_ops = {
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/* probe and remove */
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.probe = hda_dsp_probe,
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.remove = hda_dsp_remove,
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/* Register IO */
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.write = sof_io_write,
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.read = sof_io_read,
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.write64 = sof_io_write64,
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.read64 = sof_io_read64,
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/* Block IO */
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.block_read = sof_block_read,
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.block_write = sof_block_write,
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/* doorbell */
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.irq_handler = hda_dsp_ipc_irq_handler,
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.irq_thread = cnl_ipc_irq_thread,
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/* ipc */
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.send_msg = cnl_ipc_send_msg,
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.fw_ready = sof_fw_ready,
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.get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset,
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.get_window_offset = hda_dsp_ipc_get_window_offset,
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.ipc_msg_data = hda_ipc_msg_data,
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.ipc_pcm_params = hda_ipc_pcm_params,
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/* debug */
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.debug_map = cnl_dsp_debugfs,
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.debug_map_count = ARRAY_SIZE(cnl_dsp_debugfs),
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.dbg_dump = hda_dsp_dump,
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.ipc_dump = cnl_ipc_dump,
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/* stream callbacks */
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.pcm_open = hda_dsp_pcm_open,
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.pcm_close = hda_dsp_pcm_close,
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.pcm_hw_params = hda_dsp_pcm_hw_params,
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.pcm_hw_free = hda_dsp_stream_hw_free,
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.pcm_trigger = hda_dsp_pcm_trigger,
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.pcm_pointer = hda_dsp_pcm_pointer,
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/* firmware loading */
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.load_firmware = snd_sof_load_firmware_raw,
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/* pre/post fw run */
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.pre_fw_run = hda_dsp_pre_fw_run,
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.post_fw_run = hda_dsp_post_fw_run,
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/* dsp core power up/down */
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.core_power_up = hda_dsp_enable_core,
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.core_power_down = hda_dsp_core_reset_power_down,
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/* firmware run */
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.run = hda_dsp_cl_boot_firmware,
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/* trace callback */
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.trace_init = hda_dsp_trace_init,
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.trace_release = hda_dsp_trace_release,
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.trace_trigger = hda_dsp_trace_trigger,
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/* DAI drivers */
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.drv = skl_dai,
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.num_drv = SOF_SKL_NUM_DAIS,
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/* PM */
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.suspend = hda_dsp_suspend,
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.resume = hda_dsp_resume,
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.runtime_suspend = hda_dsp_runtime_suspend,
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.runtime_resume = hda_dsp_runtime_resume,
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.runtime_idle = hda_dsp_runtime_idle,
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.set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume,
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};
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EXPORT_SYMBOL(sof_cnl_ops);
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const struct sof_intel_dsp_desc cnl_chip_info = {
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/* Cannonlake */
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.cores_num = 4,
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.init_core_mask = 1,
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.cores_mask = HDA_DSP_CORE_MASK(0) |
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HDA_DSP_CORE_MASK(1) |
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HDA_DSP_CORE_MASK(2) |
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HDA_DSP_CORE_MASK(3),
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.ipc_req = CNL_DSP_REG_HIPCIDR,
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
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.ipc_ack = CNL_DSP_REG_HIPCIDA,
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.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
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.ipc_ctl = CNL_DSP_REG_HIPCCTL,
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.rom_init_timeout = 300,
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.ssp_count = CNL_SSP_COUNT,
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.ssp_base_offset = CNL_SSP_BASE_OFFSET,
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};
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EXPORT_SYMBOL(cnl_chip_info);
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const struct sof_intel_dsp_desc icl_chip_info = {
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/* Icelake */
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.cores_num = 4,
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.init_core_mask = 1,
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.cores_mask = HDA_DSP_CORE_MASK(0) |
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HDA_DSP_CORE_MASK(1) |
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HDA_DSP_CORE_MASK(2) |
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HDA_DSP_CORE_MASK(3),
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.ipc_req = CNL_DSP_REG_HIPCIDR,
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
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.ipc_ack = CNL_DSP_REG_HIPCIDA,
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.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
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.ipc_ctl = CNL_DSP_REG_HIPCCTL,
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.rom_init_timeout = 300,
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.ssp_count = ICL_SSP_COUNT,
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.ssp_base_offset = CNL_SSP_BASE_OFFSET,
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};
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EXPORT_SYMBOL(icl_chip_info);
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const struct sof_intel_dsp_desc tgl_chip_info = {
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/* Tigerlake */
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.cores_num = 4,
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.init_core_mask = 1,
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.cores_mask = HDA_DSP_CORE_MASK(0),
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.ipc_req = CNL_DSP_REG_HIPCIDR,
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
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.ipc_ack = CNL_DSP_REG_HIPCIDA,
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.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
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.ipc_ctl = CNL_DSP_REG_HIPCCTL,
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.rom_init_timeout = 300,
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.ssp_count = ICL_SSP_COUNT,
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.ssp_base_offset = CNL_SSP_BASE_OFFSET,
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};
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EXPORT_SYMBOL(tgl_chip_info);
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const struct sof_intel_dsp_desc ehl_chip_info = {
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/* Elkhartlake */
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.cores_num = 4,
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.init_core_mask = 1,
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.cores_mask = HDA_DSP_CORE_MASK(0),
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.ipc_req = CNL_DSP_REG_HIPCIDR,
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
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.ipc_ack = CNL_DSP_REG_HIPCIDA,
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.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
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.ipc_ctl = CNL_DSP_REG_HIPCCTL,
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.rom_init_timeout = 300,
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.ssp_count = ICL_SSP_COUNT,
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.ssp_base_offset = CNL_SSP_BASE_OFFSET,
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};
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EXPORT_SYMBOL(ehl_chip_info);
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