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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 503 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Enrico Weigelt <info@metux.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190602204653.811534538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
489 lines
12 KiB
C
489 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2009 Nokia Corporation
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* Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
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*
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* Some code and ideas taken from drivers/video/omap/ driver
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* by Imre Deak.
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*/
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#ifndef __OMAP2_DSS_H
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#define __OMAP2_DSS_H
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#include <linux/interrupt.h>
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#include "omapdss.h"
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struct dispc_device;
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struct dss_debugfs_entry;
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struct platform_device;
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struct seq_file;
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#define MAX_DSS_LCD_MANAGERS 3
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#define MAX_NUM_DSI 2
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#ifdef pr_fmt
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#undef pr_fmt
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#endif
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#ifdef DSS_SUBSYS_NAME
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#define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
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#else
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#define pr_fmt(fmt) fmt
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#endif
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#define DSSDBG(format, ...) \
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pr_debug(format, ## __VA_ARGS__)
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#ifdef DSS_SUBSYS_NAME
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#define DSSERR(format, ...) \
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pr_err("omapdss " DSS_SUBSYS_NAME " error: " format, ##__VA_ARGS__)
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#else
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#define DSSERR(format, ...) \
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pr_err("omapdss error: " format, ##__VA_ARGS__)
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#endif
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#ifdef DSS_SUBSYS_NAME
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#define DSSINFO(format, ...) \
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pr_info("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__)
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#else
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#define DSSINFO(format, ...) \
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pr_info("omapdss: " format, ## __VA_ARGS__)
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#endif
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#ifdef DSS_SUBSYS_NAME
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#define DSSWARN(format, ...) \
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pr_warn("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__)
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#else
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#define DSSWARN(format, ...) \
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pr_warn("omapdss: " format, ##__VA_ARGS__)
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#endif
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/* OMAP TRM gives bitfields as start:end, where start is the higher bit
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number. For example 7:0 */
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#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
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#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
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#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
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#define FLD_MOD(orig, val, start, end) \
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(((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
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enum dss_model {
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DSS_MODEL_OMAP2,
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DSS_MODEL_OMAP3,
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DSS_MODEL_OMAP4,
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DSS_MODEL_OMAP5,
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DSS_MODEL_DRA7,
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};
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enum dss_io_pad_mode {
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DSS_IO_PAD_MODE_RESET,
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DSS_IO_PAD_MODE_RFBI,
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DSS_IO_PAD_MODE_BYPASS,
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};
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enum dss_hdmi_venc_clk_source_select {
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DSS_VENC_TV_CLK = 0,
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DSS_HDMI_M_PCLK = 1,
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};
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enum dss_dsi_content_type {
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DSS_DSI_CONTENT_DCS,
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DSS_DSI_CONTENT_GENERIC,
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};
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enum dss_clk_source {
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DSS_CLK_SRC_FCK = 0,
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DSS_CLK_SRC_PLL1_1,
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DSS_CLK_SRC_PLL1_2,
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DSS_CLK_SRC_PLL1_3,
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DSS_CLK_SRC_PLL2_1,
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DSS_CLK_SRC_PLL2_2,
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DSS_CLK_SRC_PLL2_3,
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DSS_CLK_SRC_HDMI_PLL,
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};
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enum dss_pll_id {
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DSS_PLL_DSI1,
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DSS_PLL_DSI2,
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DSS_PLL_HDMI,
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DSS_PLL_VIDEO1,
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DSS_PLL_VIDEO2,
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};
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struct dss_pll;
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#define DSS_PLL_MAX_HSDIVS 4
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enum dss_pll_type {
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DSS_PLL_TYPE_A,
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DSS_PLL_TYPE_B,
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};
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/*
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* Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
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* Type-B PLLs: clkout[0] refers to m2.
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*/
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struct dss_pll_clock_info {
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/* rates that we get with dividers below */
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unsigned long fint;
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unsigned long clkdco;
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unsigned long clkout[DSS_PLL_MAX_HSDIVS];
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/* dividers */
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u16 n;
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u16 m;
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u32 mf;
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u16 mX[DSS_PLL_MAX_HSDIVS];
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u16 sd;
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};
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struct dss_pll_ops {
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int (*enable)(struct dss_pll *pll);
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void (*disable)(struct dss_pll *pll);
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int (*set_config)(struct dss_pll *pll,
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const struct dss_pll_clock_info *cinfo);
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};
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struct dss_pll_hw {
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enum dss_pll_type type;
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unsigned int n_max;
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unsigned int m_min;
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unsigned int m_max;
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unsigned int mX_max;
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unsigned long fint_min, fint_max;
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unsigned long clkdco_min, clkdco_low, clkdco_max;
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u8 n_msb, n_lsb;
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u8 m_msb, m_lsb;
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u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];
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bool has_stopmode;
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bool has_freqsel;
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bool has_selfreqdco;
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bool has_refsel;
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/* DRA7 errata i886: use high N & M to avoid jitter */
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bool errata_i886;
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/* DRA7 errata i932: retry pll lock on failure */
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bool errata_i932;
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};
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struct dss_pll {
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const char *name;
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enum dss_pll_id id;
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struct dss_device *dss;
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struct clk *clkin;
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struct regulator *regulator;
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void __iomem *base;
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const struct dss_pll_hw *hw;
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const struct dss_pll_ops *ops;
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struct dss_pll_clock_info cinfo;
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};
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/* Defines a generic omap register field */
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struct dss_reg_field {
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u8 start, end;
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};
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struct dispc_clock_info {
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/* rates that we get with dividers below */
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unsigned long lck;
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unsigned long pck;
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/* dividers */
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u16 lck_div;
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u16 pck_div;
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};
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struct dss_lcd_mgr_config {
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enum dss_io_pad_mode io_pad_mode;
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bool stallmode;
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bool fifohandcheck;
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struct dispc_clock_info clock_info;
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int video_port_width;
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int lcden_sig_polarity;
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};
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#define DSS_SZ_REGS SZ_512
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struct dss_device {
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struct platform_device *pdev;
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void __iomem *base;
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struct regmap *syscon_pll_ctrl;
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u32 syscon_pll_ctrl_offset;
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struct platform_device *drm_pdev;
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struct clk *parent_clk;
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struct clk *dss_clk;
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unsigned long dss_clk_rate;
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unsigned long cache_req_pck;
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unsigned long cache_prate;
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struct dispc_clock_info cache_dispc_cinfo;
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enum dss_clk_source dsi_clk_source[MAX_NUM_DSI];
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enum dss_clk_source dispc_clk_source;
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enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
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bool ctx_valid;
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u32 ctx[DSS_SZ_REGS / sizeof(u32)];
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const struct dss_features *feat;
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struct {
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struct dentry *root;
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struct dss_debugfs_entry *clk;
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struct dss_debugfs_entry *dss;
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} debugfs;
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struct dss_pll *plls[4];
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struct dss_pll *video1_pll;
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struct dss_pll *video2_pll;
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struct dispc_device *dispc;
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const struct dispc_ops *dispc_ops;
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const struct dss_mgr_ops *mgr_ops;
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struct omap_drm_private *mgr_ops_priv;
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};
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/* core */
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static inline int dss_set_min_bus_tput(struct device *dev, unsigned long tput)
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{
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/* To be implemented when the OMAP platform will provide this feature */
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return 0;
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}
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static inline bool dss_mgr_is_lcd(enum omap_channel id)
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{
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if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
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id == OMAP_DSS_CHANNEL_LCD3)
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return true;
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else
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return false;
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}
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/* DSS */
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#if defined(CONFIG_OMAP2_DSS_DEBUGFS)
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struct dss_debugfs_entry *
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dss_debugfs_create_file(struct dss_device *dss, const char *name,
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int (*show_fn)(struct seq_file *s, void *data),
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void *data);
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void dss_debugfs_remove_file(struct dss_debugfs_entry *entry);
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#else
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static inline struct dss_debugfs_entry *
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dss_debugfs_create_file(struct dss_device *dss, const char *name,
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int (*show_fn)(struct seq_file *s, void *data),
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void *data)
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{
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return NULL;
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}
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static inline void dss_debugfs_remove_file(struct dss_debugfs_entry *entry)
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{
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}
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#endif /* CONFIG_OMAP2_DSS_DEBUGFS */
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struct dss_device *dss_get_device(struct device *dev);
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int dss_runtime_get(struct dss_device *dss);
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void dss_runtime_put(struct dss_device *dss);
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unsigned long dss_get_dispc_clk_rate(struct dss_device *dss);
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unsigned long dss_get_max_fck_rate(struct dss_device *dss);
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int dss_dpi_select_source(struct dss_device *dss, int port,
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enum omap_channel channel);
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void dss_select_hdmi_venc_clk_source(struct dss_device *dss,
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enum dss_hdmi_venc_clk_source_select src);
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const char *dss_get_clk_source_name(enum dss_clk_source clk_src);
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/* DSS VIDEO PLL */
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struct dss_pll *dss_video_pll_init(struct dss_device *dss,
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struct platform_device *pdev, int id,
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struct regulator *regulator);
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void dss_video_pll_uninit(struct dss_pll *pll);
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void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable);
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void dss_sdi_init(struct dss_device *dss, int datapairs);
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int dss_sdi_enable(struct dss_device *dss);
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void dss_sdi_disable(struct dss_device *dss);
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void dss_select_dsi_clk_source(struct dss_device *dss, int dsi_module,
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enum dss_clk_source clk_src);
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void dss_select_lcd_clk_source(struct dss_device *dss,
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enum omap_channel channel,
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enum dss_clk_source clk_src);
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enum dss_clk_source dss_get_dispc_clk_source(struct dss_device *dss);
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enum dss_clk_source dss_get_dsi_clk_source(struct dss_device *dss,
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int dsi_module);
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enum dss_clk_source dss_get_lcd_clk_source(struct dss_device *dss,
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enum omap_channel channel);
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void dss_set_venc_output(struct dss_device *dss, enum omap_dss_venc_type type);
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void dss_set_dac_pwrdn_bgz(struct dss_device *dss, bool enable);
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int dss_set_fck_rate(struct dss_device *dss, unsigned long rate);
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typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
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bool dss_div_calc(struct dss_device *dss, unsigned long pck,
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unsigned long fck_min, dss_div_calc_func func, void *data);
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/* SDI */
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#ifdef CONFIG_OMAP2_DSS_SDI
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int sdi_init_port(struct dss_device *dss, struct platform_device *pdev,
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struct device_node *port);
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void sdi_uninit_port(struct device_node *port);
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#else
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static inline int sdi_init_port(struct dss_device *dss,
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struct platform_device *pdev,
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struct device_node *port)
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{
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return 0;
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}
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static inline void sdi_uninit_port(struct device_node *port)
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{
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}
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#endif
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/* DSI */
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#ifdef CONFIG_OMAP2_DSS_DSI
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void dsi_irq_handler(void);
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#endif
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/* DPI */
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#ifdef CONFIG_OMAP2_DSS_DPI
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int dpi_init_port(struct dss_device *dss, struct platform_device *pdev,
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struct device_node *port, enum dss_model dss_model);
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void dpi_uninit_port(struct device_node *port);
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#else
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static inline int dpi_init_port(struct dss_device *dss,
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struct platform_device *pdev,
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struct device_node *port,
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enum dss_model dss_model)
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{
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return 0;
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}
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static inline void dpi_uninit_port(struct device_node *port)
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{
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}
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#endif
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/* DISPC */
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void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s);
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int dispc_runtime_get(struct dispc_device *dispc);
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void dispc_runtime_put(struct dispc_device *dispc);
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void dispc_enable_sidle(struct dispc_device *dispc);
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void dispc_disable_sidle(struct dispc_device *dispc);
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void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable);
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void dispc_pck_free_enable(struct dispc_device *dispc, bool enable);
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void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable);
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typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
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unsigned long pck, void *data);
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bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq,
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unsigned long pck_min, unsigned long pck_max,
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dispc_div_calc_func func, void *data);
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int dispc_calc_clock_rates(struct dispc_device *dispc,
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unsigned long dispc_fclk_rate,
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struct dispc_clock_info *cinfo);
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void dispc_ovl_set_fifo_threshold(struct dispc_device *dispc,
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enum omap_plane_id plane, u32 low, u32 high);
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void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc,
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enum omap_plane_id plane,
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u32 *fifo_low, u32 *fifo_high,
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bool use_fifomerge, bool manual_update);
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void dispc_mgr_set_clock_div(struct dispc_device *dispc,
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enum omap_channel channel,
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const struct dispc_clock_info *cinfo);
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int dispc_mgr_get_clock_div(struct dispc_device *dispc,
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enum omap_channel channel,
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struct dispc_clock_info *cinfo);
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void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk);
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#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
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static inline void dss_collect_irq_stats(u32 irqstatus, unsigned int *irq_arr)
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{
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int b;
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for (b = 0; b < 32; ++b) {
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if (irqstatus & (1 << b))
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irq_arr[b]++;
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}
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}
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#endif
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/* PLL */
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typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
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unsigned long clkdco, void *data);
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typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
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void *data);
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int dss_pll_register(struct dss_device *dss, struct dss_pll *pll);
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void dss_pll_unregister(struct dss_pll *pll);
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struct dss_pll *dss_pll_find(struct dss_device *dss, const char *name);
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struct dss_pll *dss_pll_find_by_src(struct dss_device *dss,
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enum dss_clk_source src);
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unsigned int dss_pll_get_clkout_idx_for_src(enum dss_clk_source src);
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int dss_pll_enable(struct dss_pll *pll);
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void dss_pll_disable(struct dss_pll *pll);
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int dss_pll_set_config(struct dss_pll *pll,
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const struct dss_pll_clock_info *cinfo);
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bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco,
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unsigned long out_min, unsigned long out_max,
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dss_hsdiv_calc_func func, void *data);
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bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
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unsigned long pll_min, unsigned long pll_max,
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dss_pll_calc_func func, void *data);
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bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
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unsigned long target_clkout, struct dss_pll_clock_info *cinfo);
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int dss_pll_write_config_type_a(struct dss_pll *pll,
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const struct dss_pll_clock_info *cinfo);
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int dss_pll_write_config_type_b(struct dss_pll *pll,
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const struct dss_pll_clock_info *cinfo);
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int dss_pll_wait_reset_done(struct dss_pll *pll);
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extern struct platform_driver omap_dsshw_driver;
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extern struct platform_driver omap_dispchw_driver;
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#ifdef CONFIG_OMAP2_DSS_DSI
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extern struct platform_driver omap_dsihw_driver;
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#endif
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#ifdef CONFIG_OMAP2_DSS_VENC
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extern struct platform_driver omap_venchw_driver;
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#endif
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#ifdef CONFIG_OMAP4_DSS_HDMI
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extern struct platform_driver omapdss_hdmi4hw_driver;
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#endif
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#ifdef CONFIG_OMAP5_DSS_HDMI
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extern struct platform_driver omapdss_hdmi5hw_driver;
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#endif
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#endif
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