mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-09 10:36:40 +07:00
492a426a2f
Implement gamma_lut atomic crtc properties, set crtc gamma size to 256 for all crtcs and use drm_atomic_helper_legacy_gamma_set() as gamma_set func. The tv-out crtc has 1024 element gamma table (with 10bit precision) in HW, but current Xorg server does not accept anything else but 256 elements so that is used for all CRTCs. The dss dispc API converts table of any length for HW and uses linear interpolation in the process. The default gamma table is restored if gamma_lut property is deleted. Signed-off-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
599 lines
15 KiB
C
599 lines
15 KiB
C
/*
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* drivers/gpu/drm/omapdrm/omap_crtc.c
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*
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* Copyright (C) 2011 Texas Instruments
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* Author: Rob Clark <rob@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_mode.h>
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#include <drm/drm_plane_helper.h>
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#include "omap_drv.h"
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#define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
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struct omap_crtc {
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struct drm_crtc base;
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const char *name;
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enum omap_channel channel;
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struct omap_video_timings timings;
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struct omap_drm_irq vblank_irq;
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struct omap_drm_irq error_irq;
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bool ignore_digit_sync_lost;
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bool pending;
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wait_queue_head_t pending_wait;
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};
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/* -----------------------------------------------------------------------------
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* Helper Functions
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*/
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uint32_t pipe2vbl(struct drm_crtc *crtc)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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return dispc_mgr_get_vsync_irq(omap_crtc->channel);
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}
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struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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return &omap_crtc->timings;
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}
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enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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return omap_crtc->channel;
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}
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int omap_crtc_wait_pending(struct drm_crtc *crtc)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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/*
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* Timeout is set to a "sufficiently" high value, which should cover
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* a single frame refresh even on slower displays.
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*/
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return wait_event_timeout(omap_crtc->pending_wait,
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!omap_crtc->pending,
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msecs_to_jiffies(250));
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}
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/* -----------------------------------------------------------------------------
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* DSS Manager Functions
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*/
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/*
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* Manager-ops, callbacks from output when they need to configure
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* the upstream part of the video pipe.
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*
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* Most of these we can ignore until we add support for command-mode
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* panels.. for video-mode the crtc-helpers already do an adequate
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* job of sequencing the setup of the video pipe in the proper order
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*/
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/* ovl-mgr-id -> crtc */
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static struct omap_crtc *omap_crtcs[8];
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static struct omap_dss_device *omap_crtc_output[8];
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/* we can probably ignore these until we support command-mode panels: */
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static int omap_crtc_dss_connect(enum omap_channel channel,
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struct omap_dss_device *dst)
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{
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if (omap_crtc_output[channel])
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return -EINVAL;
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if ((dispc_mgr_get_supported_outputs(channel) & dst->id) == 0)
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return -EINVAL;
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omap_crtc_output[channel] = dst;
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dst->dispc_channel_connected = true;
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return 0;
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}
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static void omap_crtc_dss_disconnect(enum omap_channel channel,
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struct omap_dss_device *dst)
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{
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omap_crtc_output[channel] = NULL;
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dst->dispc_channel_connected = false;
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}
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static void omap_crtc_dss_start_update(enum omap_channel channel)
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{
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}
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/* Called only from the encoder enable/disable and suspend/resume handlers. */
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static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
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{
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struct drm_device *dev = crtc->dev;
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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enum omap_channel channel = omap_crtc->channel;
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struct omap_irq_wait *wait;
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u32 framedone_irq, vsync_irq;
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int ret;
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if (omap_crtc_output[channel]->output_type == OMAP_DISPLAY_TYPE_HDMI) {
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dispc_mgr_enable(channel, enable);
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return;
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}
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if (dispc_mgr_is_enabled(channel) == enable)
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return;
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if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
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/*
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* Digit output produces some sync lost interrupts during the
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* first frame when enabling, so we need to ignore those.
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*/
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omap_crtc->ignore_digit_sync_lost = true;
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}
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framedone_irq = dispc_mgr_get_framedone_irq(channel);
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vsync_irq = dispc_mgr_get_vsync_irq(channel);
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if (enable) {
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wait = omap_irq_wait_init(dev, vsync_irq, 1);
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} else {
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/*
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* When we disable the digit output, we need to wait for
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* FRAMEDONE to know that DISPC has finished with the output.
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*
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* OMAP2/3 does not have FRAMEDONE irq for digit output, and in
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* that case we need to use vsync interrupt, and wait for both
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* even and odd frames.
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*/
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if (framedone_irq)
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wait = omap_irq_wait_init(dev, framedone_irq, 1);
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else
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wait = omap_irq_wait_init(dev, vsync_irq, 2);
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}
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dispc_mgr_enable(channel, enable);
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ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
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if (ret) {
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dev_err(dev->dev, "%s: timeout waiting for %s\n",
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omap_crtc->name, enable ? "enable" : "disable");
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}
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if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
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omap_crtc->ignore_digit_sync_lost = false;
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/* make sure the irq handler sees the value above */
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mb();
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}
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}
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static int omap_crtc_dss_enable(enum omap_channel channel)
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{
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struct omap_crtc *omap_crtc = omap_crtcs[channel];
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struct omap_overlay_manager_info info;
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memset(&info, 0, sizeof(info));
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info.default_color = 0x00000000;
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info.trans_key = 0x00000000;
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info.trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
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info.trans_enabled = false;
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dispc_mgr_setup(omap_crtc->channel, &info);
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dispc_mgr_set_timings(omap_crtc->channel,
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&omap_crtc->timings);
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omap_crtc_set_enabled(&omap_crtc->base, true);
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return 0;
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}
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static void omap_crtc_dss_disable(enum omap_channel channel)
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{
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struct omap_crtc *omap_crtc = omap_crtcs[channel];
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omap_crtc_set_enabled(&omap_crtc->base, false);
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}
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static void omap_crtc_dss_set_timings(enum omap_channel channel,
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const struct omap_video_timings *timings)
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{
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struct omap_crtc *omap_crtc = omap_crtcs[channel];
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DBG("%s", omap_crtc->name);
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omap_crtc->timings = *timings;
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}
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static void omap_crtc_dss_set_lcd_config(enum omap_channel channel,
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const struct dss_lcd_mgr_config *config)
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{
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struct omap_crtc *omap_crtc = omap_crtcs[channel];
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DBG("%s", omap_crtc->name);
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dispc_mgr_set_lcd_config(omap_crtc->channel, config);
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}
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static int omap_crtc_dss_register_framedone(
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enum omap_channel channel,
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void (*handler)(void *), void *data)
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{
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return 0;
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}
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static void omap_crtc_dss_unregister_framedone(
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enum omap_channel channel,
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void (*handler)(void *), void *data)
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{
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}
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static const struct dss_mgr_ops mgr_ops = {
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.connect = omap_crtc_dss_connect,
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.disconnect = omap_crtc_dss_disconnect,
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.start_update = omap_crtc_dss_start_update,
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.enable = omap_crtc_dss_enable,
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.disable = omap_crtc_dss_disable,
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.set_timings = omap_crtc_dss_set_timings,
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.set_lcd_config = omap_crtc_dss_set_lcd_config,
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.register_framedone_handler = omap_crtc_dss_register_framedone,
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.unregister_framedone_handler = omap_crtc_dss_unregister_framedone,
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};
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/* -----------------------------------------------------------------------------
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* Setup, Flush and Page Flip
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*/
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static void omap_crtc_complete_page_flip(struct drm_crtc *crtc)
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{
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struct drm_pending_vblank_event *event;
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struct drm_device *dev = crtc->dev;
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unsigned long flags;
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event = crtc->state->event;
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if (!event)
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return;
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spin_lock_irqsave(&dev->event_lock, flags);
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drm_crtc_send_vblank_event(crtc, event);
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spin_unlock_irqrestore(&dev->event_lock, flags);
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}
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static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
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{
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struct omap_crtc *omap_crtc =
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container_of(irq, struct omap_crtc, error_irq);
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if (omap_crtc->ignore_digit_sync_lost) {
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irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
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if (!irqstatus)
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return;
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}
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DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);
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}
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static void omap_crtc_vblank_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
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{
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struct omap_crtc *omap_crtc =
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container_of(irq, struct omap_crtc, vblank_irq);
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struct drm_device *dev = omap_crtc->base.dev;
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if (dispc_mgr_go_busy(omap_crtc->channel))
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return;
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DBG("%s: apply done", omap_crtc->name);
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__omap_irq_unregister(dev, &omap_crtc->vblank_irq);
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rmb();
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WARN_ON(!omap_crtc->pending);
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omap_crtc->pending = false;
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wmb();
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/* wake up userspace */
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omap_crtc_complete_page_flip(&omap_crtc->base);
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/* wake up omap_atomic_complete */
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wake_up(&omap_crtc->pending_wait);
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}
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/* -----------------------------------------------------------------------------
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* CRTC Functions
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*/
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static void omap_crtc_destroy(struct drm_crtc *crtc)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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DBG("%s", omap_crtc->name);
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WARN_ON(omap_crtc->vblank_irq.registered);
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omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
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drm_crtc_cleanup(crtc);
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kfree(omap_crtc);
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}
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static void omap_crtc_enable(struct drm_crtc *crtc)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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DBG("%s", omap_crtc->name);
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rmb();
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WARN_ON(omap_crtc->pending);
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omap_crtc->pending = true;
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wmb();
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omap_irq_register(crtc->dev, &omap_crtc->vblank_irq);
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drm_crtc_vblank_on(crtc);
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}
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static void omap_crtc_disable(struct drm_crtc *crtc)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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DBG("%s", omap_crtc->name);
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drm_crtc_vblank_off(crtc);
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}
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static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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struct drm_display_mode *mode = &crtc->state->adjusted_mode;
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DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
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omap_crtc->name, mode->base.id, mode->name,
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mode->vrefresh, mode->clock,
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mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal,
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mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal,
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mode->type, mode->flags);
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copy_timings_drm_to_omap(&omap_crtc->timings, mode);
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}
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static int omap_crtc_atomic_check(struct drm_crtc *crtc,
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struct drm_crtc_state *state)
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{
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if (state->color_mgmt_changed && state->gamma_lut) {
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uint length = state->gamma_lut->length /
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sizeof(struct drm_color_lut);
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if (length < 2)
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return -EINVAL;
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}
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return 0;
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}
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static void omap_crtc_atomic_begin(struct drm_crtc *crtc,
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struct drm_crtc_state *old_crtc_state)
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{
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}
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static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
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struct drm_crtc_state *old_crtc_state)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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WARN_ON(omap_crtc->vblank_irq.registered);
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if (crtc->state->color_mgmt_changed) {
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struct drm_color_lut *lut = NULL;
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uint length = 0;
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if (crtc->state->gamma_lut) {
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lut = (struct drm_color_lut *)
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crtc->state->gamma_lut->data;
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length = crtc->state->gamma_lut->length /
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sizeof(*lut);
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}
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dispc_mgr_set_gamma(omap_crtc->channel, lut, length);
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}
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if (crtc->state->color_mgmt_changed) {
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struct drm_color_lut *lut = NULL;
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uint length = 0;
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if (crtc->state->gamma_lut) {
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lut = (struct drm_color_lut *)
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crtc->state->gamma_lut->data;
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length = crtc->state->gamma_lut->length /
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sizeof(*lut);
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}
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dispc_mgr_set_gamma(omap_crtc->channel, lut, length);
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}
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if (dispc_mgr_is_enabled(omap_crtc->channel)) {
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DBG("%s: GO", omap_crtc->name);
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rmb();
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WARN_ON(omap_crtc->pending);
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omap_crtc->pending = true;
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wmb();
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dispc_mgr_go(omap_crtc->channel);
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omap_irq_register(crtc->dev, &omap_crtc->vblank_irq);
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}
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}
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static bool omap_crtc_is_plane_prop(struct drm_device *dev,
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struct drm_property *property)
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{
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struct omap_drm_private *priv = dev->dev_private;
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return property == priv->zorder_prop ||
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property == dev->mode_config.rotation_property;
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}
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static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
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struct drm_crtc_state *state,
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struct drm_property *property,
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uint64_t val)
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{
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struct drm_device *dev = crtc->dev;
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if (omap_crtc_is_plane_prop(dev, property)) {
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struct drm_plane_state *plane_state;
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struct drm_plane *plane = crtc->primary;
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/*
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* Delegate property set to the primary plane. Get the plane
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* state and set the property directly.
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*/
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plane_state = drm_atomic_get_plane_state(state->state, plane);
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if (IS_ERR(plane_state))
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return PTR_ERR(plane_state);
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return drm_atomic_plane_set_property(plane, plane_state,
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property, val);
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}
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return -EINVAL;
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}
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static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
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const struct drm_crtc_state *state,
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struct drm_property *property,
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uint64_t *val)
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{
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struct drm_device *dev = crtc->dev;
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if (omap_crtc_is_plane_prop(dev, property)) {
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/*
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* Delegate property get to the primary plane. The
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* drm_atomic_plane_get_property() function isn't exported, but
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* can be called through drm_object_property_get_value() as that
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* will call drm_atomic_get_property() for atomic drivers.
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*/
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return drm_object_property_get_value(&crtc->primary->base,
|
|
property, val);
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static const struct drm_crtc_funcs omap_crtc_funcs = {
|
|
.reset = drm_atomic_helper_crtc_reset,
|
|
.set_config = drm_atomic_helper_set_config,
|
|
.destroy = omap_crtc_destroy,
|
|
.page_flip = drm_atomic_helper_page_flip,
|
|
.gamma_set = drm_atomic_helper_legacy_gamma_set,
|
|
.set_property = drm_atomic_helper_crtc_set_property,
|
|
.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
|
|
.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
|
|
.atomic_set_property = omap_crtc_atomic_set_property,
|
|
.atomic_get_property = omap_crtc_atomic_get_property,
|
|
};
|
|
|
|
static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
|
|
.mode_set_nofb = omap_crtc_mode_set_nofb,
|
|
.disable = omap_crtc_disable,
|
|
.enable = omap_crtc_enable,
|
|
.atomic_check = omap_crtc_atomic_check,
|
|
.atomic_begin = omap_crtc_atomic_begin,
|
|
.atomic_flush = omap_crtc_atomic_flush,
|
|
};
|
|
|
|
/* -----------------------------------------------------------------------------
|
|
* Init and Cleanup
|
|
*/
|
|
|
|
static const char *channel_names[] = {
|
|
[OMAP_DSS_CHANNEL_LCD] = "lcd",
|
|
[OMAP_DSS_CHANNEL_DIGIT] = "tv",
|
|
[OMAP_DSS_CHANNEL_LCD2] = "lcd2",
|
|
[OMAP_DSS_CHANNEL_LCD3] = "lcd3",
|
|
};
|
|
|
|
void omap_crtc_pre_init(void)
|
|
{
|
|
dss_install_mgr_ops(&mgr_ops);
|
|
}
|
|
|
|
void omap_crtc_pre_uninit(void)
|
|
{
|
|
dss_uninstall_mgr_ops();
|
|
}
|
|
|
|
/* initialize crtc */
|
|
struct drm_crtc *omap_crtc_init(struct drm_device *dev,
|
|
struct drm_plane *plane, enum omap_channel channel, int id)
|
|
{
|
|
struct drm_crtc *crtc = NULL;
|
|
struct omap_crtc *omap_crtc;
|
|
int ret;
|
|
|
|
DBG("%s", channel_names[channel]);
|
|
|
|
omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
|
|
if (!omap_crtc)
|
|
return NULL;
|
|
|
|
crtc = &omap_crtc->base;
|
|
|
|
init_waitqueue_head(&omap_crtc->pending_wait);
|
|
|
|
omap_crtc->channel = channel;
|
|
omap_crtc->name = channel_names[channel];
|
|
|
|
omap_crtc->vblank_irq.irqmask = pipe2vbl(crtc);
|
|
omap_crtc->vblank_irq.irq = omap_crtc_vblank_irq;
|
|
|
|
omap_crtc->error_irq.irqmask =
|
|
dispc_mgr_get_sync_lost_irq(channel);
|
|
omap_crtc->error_irq.irq = omap_crtc_error_irq;
|
|
omap_irq_register(dev, &omap_crtc->error_irq);
|
|
|
|
ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
|
|
&omap_crtc_funcs, NULL);
|
|
if (ret < 0) {
|
|
kfree(omap_crtc);
|
|
return NULL;
|
|
}
|
|
|
|
drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
|
|
|
|
/* The dispc API adapts to what ever size, but the HW supports
|
|
* 256 element gamma table for LCDs and 1024 element table for
|
|
* OMAP_DSS_CHANNEL_DIGIT. X server assumes 256 element gamma
|
|
* tables so lets use that. Size of HW gamma table can be
|
|
* extracted with dispc_mgr_gamma_size(). If it returns 0
|
|
* gamma table is not supprted.
|
|
*/
|
|
if (dispc_mgr_gamma_size(channel)) {
|
|
uint gamma_lut_size = 256;
|
|
|
|
drm_crtc_enable_color_mgmt(crtc, 0, false, gamma_lut_size);
|
|
drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size);
|
|
}
|
|
|
|
omap_plane_install_properties(crtc->primary, &crtc->base);
|
|
|
|
omap_crtcs[channel] = omap_crtc;
|
|
|
|
return crtc;
|
|
}
|