mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-07 03:56:41 +07:00
30c67e93c5
The usual selection of bug fixes and driver updates for GPIO. Nothing really stands out except the addition of the GRGPIO driver and some enhacements to ACPI support -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJRhuKVAAoJEEFnBt12D9kB8kUP/21N7fsCxNocqoIwX8VQPfEY KsXUKRstuETHERHpGCSvMuRAEy1vee9itijrmWOiQT09jztIxg3Sed3u0RCQjQEK mV87RdAObZzm6xTIpy5sQa1bMOlc2AzYhTDDr9f1OpU+L9XMhwq03wq/i74Zij3w 7vq5BkBfGWF84TY5ZG1SNIvtw9P2MYoCHtJKvFyTJWAH05m2bHSfuvvn8vIdcUBL TuVwoeUzbYJtTJatovkh0kyMOOZEh9JVWBPBTNNLyYDmpAKQ6RwBoAi0ZznmF4mk gp88dj6iMHebi7UnlDQJD5crw16cRoMh0pa3EBAjYM0IVhfn8AvFIhma34wTs1Z/ ZuWwwHeR93cQTKwMBT1OHRCPaOdjS5riAR4WJm5Tmq9dV0sjGlbwff26U1uHH8qX mTBA+tje4bVpSHEztmXyw0AOMUv2vid5P0F/sKtEHzfURf8Yjq8xvxyvq14T3dQQ /wzmdLKbzR05phft7Xxa4yzfSy46uvxyUJQQaKdU/jlay/gJFisJXJE0cOrwTOFo SpTCmjnacr8Tlqr04Fj8f8ZgOYrg5VAOUsVE8uY0ETWRCb7iezFw7JGE3qV1kZQk N1lPBbSnIwtkdMiEmyttxpFEb5PwJxX8pUP6JfNyMbMlHoZs2247SeakhRQs/OCx goJQEGz6eeOpvq7koiJg =PwUd -----END PGP SIGNATURE----- Merge tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux Pull GPIO changes from Grant Likely: "The usual selection of bug fixes and driver updates for GPIO. Nothing really stands out except the addition of the GRGPIO driver and some enhacements to ACPI support" I'm pulling this despite the earlier mess. Let's hope it compiles these days. * tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux: (46 commits) gpio: grgpio: Add irq support gpio: grgpio: Add device driver for GRGPIO cores gpiolib-acpi: introduce acpi_get_gpio_by_index() helper GPIO: gpio-generic: remove kfree() from bgpio_remove call gpio / ACPI: Handle ACPI events in accordance with the spec gpio: lpc32xx: Fix off-by-one valid range checking for bank gpio: mcp23s08: convert driver to DT gpio/omap: force restore if context loss is not detectable gpio/omap: optimise interrupt service routine gpio/omap: remove extra context restores in *_runtime_resume() gpio/omap: free irq domain in probe() failure paths gpio: gpio-generic: Add 16 and 32 bit big endian byte order support gpio: samsung: Add terminating entry for exynos_pinctrl_ids gpio: mvebu: add dbg_show function MAX7301 GPIO: Do not force SPI speed when using OF Platform gpio: gpio-tps65910.c: fix checkpatch error gpio: gpio-timberdale.c: fix checkpatch error gpio: gpio-tc3589x.c: fix checkpatch errors gpio: gpio-stp-xway.c: fix checkpatch error gpio: gpio-sch.c: fix checkpatch error ...
471 lines
12 KiB
C
471 lines
12 KiB
C
/*
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* Intel ICH6-10, Series 5 and 6 GPIO driver
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*
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* Copyright (C) 2010 Extreme Engineering Solutions.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <linux/mfd/lpc_ich.h>
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#define DRV_NAME "gpio_ich"
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/*
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* GPIO register offsets in GPIO I/O space.
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* Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
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* LVLx registers. Logic in the read/write functions takes a register and
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* an absolute bit number and determines the proper register offset and bit
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* number in that register. For example, to read the value of GPIO bit 50
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* the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
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* bit 18 (50%32).
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*/
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enum GPIO_REG {
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GPIO_USE_SEL = 0,
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GPIO_IO_SEL,
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GPIO_LVL,
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};
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static const u8 ichx_regs[3][3] = {
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{0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */
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{0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */
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{0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */
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};
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static const u8 ichx_reglen[3] = {
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0x30, 0x10, 0x10,
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};
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#define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start)
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#define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start)
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struct ichx_desc {
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/* Max GPIO pins the chipset can have */
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uint ngpio;
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/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
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bool uses_gpe0;
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/* USE_SEL is bogus on some chipsets, eg 3100 */
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u32 use_sel_ignore[3];
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/* Some chipsets have quirks, let these use their own request/get */
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int (*request)(struct gpio_chip *chip, unsigned offset);
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int (*get)(struct gpio_chip *chip, unsigned offset);
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};
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static struct {
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spinlock_t lock;
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struct platform_device *dev;
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struct gpio_chip chip;
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struct resource *gpio_base; /* GPIO IO base */
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struct resource *pm_base; /* Power Mangagment IO base */
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struct ichx_desc *desc; /* Pointer to chipset-specific description */
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u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */
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u8 use_gpio; /* Which GPIO groups are usable */
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} ichx_priv;
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static int modparam_gpiobase = -1; /* dynamic */
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module_param_named(gpiobase, modparam_gpiobase, int, 0444);
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MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, "
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"which is the default.");
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static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
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{
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unsigned long flags;
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u32 data, tmp;
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int reg_nr = nr / 32;
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int bit = nr & 0x1f;
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int ret = 0;
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spin_lock_irqsave(&ichx_priv.lock, flags);
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data = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
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if (val)
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data |= 1 << bit;
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else
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data &= ~(1 << bit);
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ICHX_WRITE(data, ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
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tmp = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
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if (verify && data != tmp)
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ret = -EPERM;
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spin_unlock_irqrestore(&ichx_priv.lock, flags);
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return ret;
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}
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static int ichx_read_bit(int reg, unsigned nr)
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{
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unsigned long flags;
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u32 data;
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int reg_nr = nr / 32;
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int bit = nr & 0x1f;
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spin_lock_irqsave(&ichx_priv.lock, flags);
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data = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
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spin_unlock_irqrestore(&ichx_priv.lock, flags);
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return data & (1 << bit) ? 1 : 0;
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}
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static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)
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{
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return !!(ichx_priv.use_gpio & (1 << (nr / 32)));
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}
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static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
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{
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/*
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* Try setting pin as an input and verify it worked since many pins
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* are output-only.
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*/
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if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1))
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return -EINVAL;
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return 0;
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}
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static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
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int val)
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{
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/* Set GPIO output value. */
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ichx_write_bit(GPIO_LVL, nr, val, 0);
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/*
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* Try setting pin as an output and verify it worked since many pins
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* are input-only.
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*/
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if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1))
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return -EINVAL;
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return 0;
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}
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static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
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{
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return ichx_read_bit(GPIO_LVL, nr);
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}
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static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
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{
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unsigned long flags;
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u32 data;
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/*
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* GPI 0 - 15 need to be read from the power management registers on
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* a ICH6/3100 bridge.
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*/
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if (nr < 16) {
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if (!ichx_priv.pm_base)
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return -ENXIO;
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spin_lock_irqsave(&ichx_priv.lock, flags);
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/* GPI 0 - 15 are latched, write 1 to clear*/
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ICHX_WRITE(1 << (16 + nr), 0, ichx_priv.pm_base);
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data = ICHX_READ(0, ichx_priv.pm_base);
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spin_unlock_irqrestore(&ichx_priv.lock, flags);
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return (data >> 16) & (1 << nr) ? 1 : 0;
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} else {
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return ichx_gpio_get(chip, nr);
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}
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}
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static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
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{
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if (!ichx_gpio_check_available(chip, nr))
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return -ENXIO;
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/*
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* Note we assume the BIOS properly set a bridge's USE value. Some
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* chips (eg Intel 3100) have bogus USE values though, so first see if
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* the chipset's USE value can be trusted for this specific bit.
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* If it can't be trusted, assume that the pin can be used as a GPIO.
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*/
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if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f)))
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return 0;
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return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
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}
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static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
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{
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/*
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* Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
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* bridge as they are controlled by USE register bits 0 and 1. See
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* "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
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* additional info.
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*/
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if (nr == 16 || nr == 17)
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nr -= 16;
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return ichx_gpio_request(chip, nr);
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}
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static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
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{
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ichx_write_bit(GPIO_LVL, nr, val, 0);
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}
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static void ichx_gpiolib_setup(struct gpio_chip *chip)
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{
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chip->owner = THIS_MODULE;
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chip->label = DRV_NAME;
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chip->dev = &ichx_priv.dev->dev;
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/* Allow chip-specific overrides of request()/get() */
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chip->request = ichx_priv.desc->request ?
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ichx_priv.desc->request : ichx_gpio_request;
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chip->get = ichx_priv.desc->get ?
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ichx_priv.desc->get : ichx_gpio_get;
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chip->set = ichx_gpio_set;
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chip->direction_input = ichx_gpio_direction_input;
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chip->direction_output = ichx_gpio_direction_output;
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chip->base = modparam_gpiobase;
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chip->ngpio = ichx_priv.desc->ngpio;
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chip->can_sleep = 0;
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chip->dbg_show = NULL;
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}
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/* ICH6-based, 631xesb-based */
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static struct ichx_desc ich6_desc = {
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/* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
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.request = ich6_gpio_request,
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.get = ich6_gpio_get,
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/* GPIO 0-15 are read in the GPE0_STS PM register */
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.uses_gpe0 = true,
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.ngpio = 50,
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};
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/* Intel 3100 */
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static struct ichx_desc i3100_desc = {
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/*
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* Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
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* the Intel 3100. See "Table 712. GPIO Summary Table" of 3100
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* Datasheet for more info.
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*/
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.use_sel_ignore = {0x00130000, 0x00010000, 0x0},
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/* The 3100 needs fixups for GPIO 0 - 17 */
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.request = ich6_gpio_request,
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.get = ich6_gpio_get,
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/* GPIO 0-15 are read in the GPE0_STS PM register */
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.uses_gpe0 = true,
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.ngpio = 50,
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};
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/* ICH7 and ICH8-based */
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static struct ichx_desc ich7_desc = {
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.ngpio = 50,
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};
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/* ICH9-based */
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static struct ichx_desc ich9_desc = {
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.ngpio = 61,
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};
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/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
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static struct ichx_desc ich10_cons_desc = {
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.ngpio = 61,
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};
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static struct ichx_desc ich10_corp_desc = {
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.ngpio = 72,
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};
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/* Intel 5 series, 6 series, 3400 series, and C200 series */
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static struct ichx_desc intel5_desc = {
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.ngpio = 76,
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};
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static int ichx_gpio_request_regions(struct resource *res_base,
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const char *name, u8 use_gpio)
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{
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int i;
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if (!res_base || !res_base->start || !res_base->end)
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return -ENODEV;
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for (i = 0; i < ARRAY_SIZE(ichx_regs[0]); i++) {
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if (!(use_gpio & (1 << i)))
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continue;
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if (!request_region(res_base->start + ichx_regs[0][i],
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ichx_reglen[i], name))
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goto request_err;
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}
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return 0;
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request_err:
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/* Clean up: release already requested regions, if any */
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for (i--; i >= 0; i--) {
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if (!(use_gpio & (1 << i)))
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continue;
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release_region(res_base->start + ichx_regs[0][i],
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ichx_reglen[i]);
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}
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return -EBUSY;
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}
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static void ichx_gpio_release_regions(struct resource *res_base, u8 use_gpio)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(ichx_regs[0]); i++) {
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if (!(use_gpio & (1 << i)))
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continue;
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release_region(res_base->start + ichx_regs[0][i],
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ichx_reglen[i]);
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}
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}
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static int ichx_gpio_probe(struct platform_device *pdev)
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{
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struct resource *res_base, *res_pm;
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int err;
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struct lpc_ich_info *ich_info = pdev->dev.platform_data;
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if (!ich_info)
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return -ENODEV;
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ichx_priv.dev = pdev;
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switch (ich_info->gpio_version) {
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case ICH_I3100_GPIO:
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ichx_priv.desc = &i3100_desc;
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break;
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case ICH_V5_GPIO:
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ichx_priv.desc = &intel5_desc;
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break;
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case ICH_V6_GPIO:
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ichx_priv.desc = &ich6_desc;
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break;
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case ICH_V7_GPIO:
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ichx_priv.desc = &ich7_desc;
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break;
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case ICH_V9_GPIO:
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ichx_priv.desc = &ich9_desc;
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break;
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case ICH_V10CORP_GPIO:
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ichx_priv.desc = &ich10_corp_desc;
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break;
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case ICH_V10CONS_GPIO:
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ichx_priv.desc = &ich10_cons_desc;
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break;
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default:
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return -ENODEV;
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}
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spin_lock_init(&ichx_priv.lock);
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res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
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ichx_priv.use_gpio = ich_info->use_gpio;
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err = ichx_gpio_request_regions(res_base, pdev->name,
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ichx_priv.use_gpio);
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if (err)
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return err;
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ichx_priv.gpio_base = res_base;
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/*
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* If necessary, determine the I/O address of ACPI/power management
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* registers which are needed to read the the GPE0 register for GPI pins
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* 0 - 15 on some chipsets.
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*/
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if (!ichx_priv.desc->uses_gpe0)
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goto init;
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res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
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if (!res_pm) {
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pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
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goto init;
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}
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if (!request_region(res_pm->start, resource_size(res_pm),
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pdev->name)) {
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pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
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goto init;
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}
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ichx_priv.pm_base = res_pm;
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init:
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ichx_gpiolib_setup(&ichx_priv.chip);
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err = gpiochip_add(&ichx_priv.chip);
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if (err) {
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pr_err("Failed to register GPIOs\n");
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goto add_err;
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}
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pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,
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ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);
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return 0;
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add_err:
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ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
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if (ichx_priv.pm_base)
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release_region(ichx_priv.pm_base->start,
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resource_size(ichx_priv.pm_base));
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return err;
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}
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static int ichx_gpio_remove(struct platform_device *pdev)
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{
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int err;
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err = gpiochip_remove(&ichx_priv.chip);
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if (err) {
|
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dev_err(&pdev->dev, "%s failed, %d\n",
|
|
"gpiochip_remove()", err);
|
|
return err;
|
|
}
|
|
|
|
ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
|
|
if (ichx_priv.pm_base)
|
|
release_region(ichx_priv.pm_base->start,
|
|
resource_size(ichx_priv.pm_base));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver ichx_gpio_driver = {
|
|
.driver = {
|
|
.owner = THIS_MODULE,
|
|
.name = DRV_NAME,
|
|
},
|
|
.probe = ichx_gpio_probe,
|
|
.remove = ichx_gpio_remove,
|
|
};
|
|
|
|
module_platform_driver(ichx_gpio_driver);
|
|
|
|
MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
|
|
MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:"DRV_NAME);
|