mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 18:45:02 +07:00
ad6afec832
Add USB 3.0 DRD controller device node, with its clock and phy information to enable the same on Exynos7. Signed-off-by: Vivek Gautam <gautamvivek1987@gmail.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
644 lines
17 KiB
Plaintext
644 lines
17 KiB
Plaintext
/*
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* SAMSUNG EXYNOS7 SoC device tree source
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*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <dt-bindings/clock/exynos7-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "samsung,exynos7";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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pinctrl0 = &pinctrl_alive;
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pinctrl1 = &pinctrl_bus0;
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pinctrl2 = &pinctrl_nfc;
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pinctrl3 = &pinctrl_touch;
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pinctrl4 = &pinctrl_ff;
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pinctrl5 = &pinctrl_ese;
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pinctrl6 = &pinctrl_fsys0;
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pinctrl7 = &pinctrl_fsys1;
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pinctrl8 = &pinctrl_bus1;
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tmuctrl0 = &tmuctrl_0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu_atlas0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x0>;
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enable-method = "psci";
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};
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cpu_atlas1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x1>;
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enable-method = "psci";
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};
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cpu_atlas2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x2>;
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enable-method = "psci";
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};
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cpu_atlas3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x3>;
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enable-method = "psci";
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0x18000000>;
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chipid@10000000 {
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compatible = "samsung,exynos4210-chipid";
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reg = <0x10000000 0x100>;
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};
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fin_pll: xxti {
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compatible = "fixed-clock";
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clock-output-names = "fin_pll";
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#clock-cells = <0>;
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};
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gic: interrupt-controller@11001000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x11001000 0x1000>,
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<0x11002000 0x1000>,
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<0x11004000 0x2000>,
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<0x11006000 0x2000>;
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pdma0: pdma@10E10000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x10E10000 0x1000>;
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock_fsys0 ACLK_PDMA0>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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};
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pdma1: pdma@10EB0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x10EB0000 0x1000>;
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interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock_fsys0 ACLK_PDMA1>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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};
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};
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clock_topc: clock-controller@10570000 {
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compatible = "samsung,exynos7-clock-topc";
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reg = <0x10570000 0x10000>;
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#clock-cells = <1>;
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};
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clock_top0: clock-controller@105d0000 {
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compatible = "samsung,exynos7-clock-top0";
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reg = <0x105d0000 0xb000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
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<&clock_topc DOUT_SCLK_BUS1_PLL>,
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<&clock_topc DOUT_SCLK_CC_PLL>,
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<&clock_topc DOUT_SCLK_MFC_PLL>;
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clock-names = "fin_pll", "dout_sclk_bus0_pll",
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"dout_sclk_bus1_pll", "dout_sclk_cc_pll",
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"dout_sclk_mfc_pll";
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};
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clock_top1: clock-controller@105e0000 {
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compatible = "samsung,exynos7-clock-top1";
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reg = <0x105e0000 0xb000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
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<&clock_topc DOUT_SCLK_BUS1_PLL>,
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<&clock_topc DOUT_SCLK_CC_PLL>,
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<&clock_topc DOUT_SCLK_MFC_PLL>;
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clock-names = "fin_pll", "dout_sclk_bus0_pll",
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"dout_sclk_bus1_pll", "dout_sclk_cc_pll",
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"dout_sclk_mfc_pll";
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};
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clock_ccore: clock-controller@105b0000 {
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compatible = "samsung,exynos7-clock-ccore";
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reg = <0x105b0000 0xd00>;
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#clock-cells = <1>;
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clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
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clock-names = "fin_pll", "dout_aclk_ccore_133";
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};
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clock_peric0: clock-controller@13610000 {
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compatible = "samsung,exynos7-clock-peric0";
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reg = <0x13610000 0xd00>;
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#clock-cells = <1>;
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clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
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<&clock_top0 CLK_SCLK_UART0>;
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clock-names = "fin_pll", "dout_aclk_peric0_66",
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"sclk_uart0";
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};
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clock_peric1: clock-controller@14c80000 {
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compatible = "samsung,exynos7-clock-peric1";
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reg = <0x14c80000 0xd00>;
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#clock-cells = <1>;
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clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
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<&clock_top0 CLK_SCLK_UART1>,
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<&clock_top0 CLK_SCLK_UART2>,
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<&clock_top0 CLK_SCLK_UART3>;
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clock-names = "fin_pll", "dout_aclk_peric1_66",
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"sclk_uart1", "sclk_uart2", "sclk_uart3";
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};
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clock_peris: clock-controller@10040000 {
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compatible = "samsung,exynos7-clock-peris";
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reg = <0x10040000 0xd00>;
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#clock-cells = <1>;
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clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>;
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clock-names = "fin_pll", "dout_aclk_peris_66";
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};
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clock_fsys0: clock-controller@10e90000 {
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compatible = "samsung,exynos7-clock-fsys0";
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reg = <0x10e90000 0xd00>;
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#clock-cells = <1>;
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clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
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<&clock_top1 DOUT_SCLK_MMC2>;
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clock-names = "fin_pll", "dout_aclk_fsys0_200",
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"dout_sclk_mmc2";
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};
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clock_fsys1: clock-controller@156e0000 {
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compatible = "samsung,exynos7-clock-fsys1";
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reg = <0x156e0000 0xd00>;
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#clock-cells = <1>;
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clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
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<&clock_top1 DOUT_SCLK_MMC0>,
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<&clock_top1 DOUT_SCLK_MMC1>;
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clock-names = "fin_pll", "dout_aclk_fsys1_200",
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"dout_sclk_mmc0", "dout_sclk_mmc1";
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};
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serial_0: serial@13630000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x13630000 0x100>;
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interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock_peric0 PCLK_UART0>,
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<&clock_peric0 SCLK_UART0>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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serial_1: serial@14c20000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x14c20000 0x100>;
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interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock_peric1 PCLK_UART1>,
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<&clock_peric1 SCLK_UART1>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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serial_2: serial@14c30000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x14c30000 0x100>;
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interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock_peric1 PCLK_UART2>,
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<&clock_peric1 SCLK_UART2>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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serial_3: serial@14c40000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x14c40000 0x100>;
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interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock_peric1 PCLK_UART3>,
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<&clock_peric1 SCLK_UART3>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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pinctrl_alive: pinctrl@10580000 {
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compatible = "samsung,exynos7-pinctrl";
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reg = <0x10580000 0x1000>;
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wakeup-interrupt-controller {
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compatible = "samsung,exynos7-wakeup-eint";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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pinctrl_bus0: pinctrl@13470000 {
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compatible = "samsung,exynos7-pinctrl";
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reg = <0x13470000 0x1000>;
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interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_nfc: pinctrl@14cd0000 {
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compatible = "samsung,exynos7-pinctrl";
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reg = <0x14cd0000 0x1000>;
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interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_touch: pinctrl@14ce0000 {
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compatible = "samsung,exynos7-pinctrl";
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reg = <0x14ce0000 0x1000>;
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interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_ff: pinctrl@14c90000 {
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compatible = "samsung,exynos7-pinctrl";
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reg = <0x14c90000 0x1000>;
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interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_ese: pinctrl@14ca0000 {
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compatible = "samsung,exynos7-pinctrl";
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reg = <0x14ca0000 0x1000>;
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interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_fsys0: pinctrl@10e60000 {
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compatible = "samsung,exynos7-pinctrl";
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reg = <0x10e60000 0x1000>;
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interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_fsys1: pinctrl@15690000 {
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compatible = "samsung,exynos7-pinctrl";
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reg = <0x15690000 0x1000>;
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interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_bus1: pinctrl@14870000 {
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compatible = "samsung,exynos7-pinctrl";
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reg = <0x14870000 0x1000>;
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interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
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};
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hsi2c_0: hsi2c@13640000 {
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compatible = "samsung,exynos7-hsi2c";
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reg = <0x13640000 0x1000>;
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interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&hs_i2c0_bus>;
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clocks = <&clock_peric0 PCLK_HSI2C0>;
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clock-names = "hsi2c";
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status = "disabled";
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};
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hsi2c_1: hsi2c@13650000 {
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compatible = "samsung,exynos7-hsi2c";
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reg = <0x13650000 0x1000>;
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interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&hs_i2c1_bus>;
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clocks = <&clock_peric0 PCLK_HSI2C1>;
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clock-names = "hsi2c";
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status = "disabled";
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};
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hsi2c_2: hsi2c@14e60000 {
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compatible = "samsung,exynos7-hsi2c";
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reg = <0x14e60000 0x1000>;
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interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&hs_i2c2_bus>;
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clocks = <&clock_peric1 PCLK_HSI2C2>;
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clock-names = "hsi2c";
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status = "disabled";
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};
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hsi2c_3: hsi2c@14e70000 {
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compatible = "samsung,exynos7-hsi2c";
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reg = <0x14e70000 0x1000>;
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interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&hs_i2c3_bus>;
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clocks = <&clock_peric1 PCLK_HSI2C3>;
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clock-names = "hsi2c";
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status = "disabled";
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};
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hsi2c_4: hsi2c@13660000 {
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compatible = "samsung,exynos7-hsi2c";
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reg = <0x13660000 0x1000>;
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interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&hs_i2c4_bus>;
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clocks = <&clock_peric0 PCLK_HSI2C4>;
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clock-names = "hsi2c";
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status = "disabled";
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};
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hsi2c_5: hsi2c@13670000 {
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compatible = "samsung,exynos7-hsi2c";
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reg = <0x13670000 0x1000>;
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interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&hs_i2c5_bus>;
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clocks = <&clock_peric0 PCLK_HSI2C5>;
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clock-names = "hsi2c";
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status = "disabled";
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};
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hsi2c_6: hsi2c@14e00000 {
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compatible = "samsung,exynos7-hsi2c";
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reg = <0x14e00000 0x1000>;
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interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&hs_i2c6_bus>;
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clocks = <&clock_peric1 PCLK_HSI2C6>;
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clock-names = "hsi2c";
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status = "disabled";
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};
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hsi2c_7: hsi2c@13e10000 {
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compatible = "samsung,exynos7-hsi2c";
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reg = <0x13e10000 0x1000>;
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interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&hs_i2c7_bus>;
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clocks = <&clock_peric1 PCLK_HSI2C7>;
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clock-names = "hsi2c";
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status = "disabled";
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};
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hsi2c_8: hsi2c@14e20000 {
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compatible = "samsung,exynos7-hsi2c";
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reg = <0x14e20000 0x1000>;
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interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&hs_i2c8_bus>;
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clocks = <&clock_peric1 PCLK_HSI2C8>;
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clock-names = "hsi2c";
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status = "disabled";
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};
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hsi2c_9: hsi2c@13680000 {
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compatible = "samsung,exynos7-hsi2c";
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reg = <0x13680000 0x1000>;
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interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
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|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hs_i2c9_bus>;
|
|
clocks = <&clock_peric0 PCLK_HSI2C9>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_10: hsi2c@13690000 {
|
|
compatible = "samsung,exynos7-hsi2c";
|
|
reg = <0x13690000 0x1000>;
|
|
interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hs_i2c10_bus>;
|
|
clocks = <&clock_peric0 PCLK_HSI2C10>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_11: hsi2c@136a0000 {
|
|
compatible = "samsung,exynos7-hsi2c";
|
|
reg = <0x136a0000 0x1000>;
|
|
interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hs_i2c11_bus>;
|
|
clocks = <&clock_peric0 PCLK_HSI2C11>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
arm-pmu {
|
|
compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
|
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
|
|
<&cpu_atlas2>, <&cpu_atlas3>;
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13
|
|
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14
|
|
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11
|
|
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10
|
|
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
|
|
pmu_system_controller: system-controller@105c0000 {
|
|
compatible = "samsung,exynos7-pmu", "syscon";
|
|
reg = <0x105c0000 0x5000>;
|
|
};
|
|
|
|
reboot: syscon-reboot {
|
|
compatible = "syscon-reboot";
|
|
regmap = <&pmu_system_controller>;
|
|
offset = <0x0400>;
|
|
mask = <0x1>;
|
|
};
|
|
|
|
rtc: rtc@10590000 {
|
|
compatible = "samsung,s3c6410-rtc";
|
|
reg = <0x10590000 0x100>;
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clock_ccore PCLK_RTC>;
|
|
clock-names = "rtc";
|
|
status = "disabled";
|
|
};
|
|
|
|
watchdog: watchdog@101d0000 {
|
|
compatible = "samsung,exynos7-wdt";
|
|
reg = <0x101d0000 0x100>;
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clock_peris PCLK_WDT>;
|
|
clock-names = "watchdog";
|
|
samsung,syscon-phandle = <&pmu_system_controller>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc_0: mmc@15740000 {
|
|
compatible = "samsung,exynos7-dw-mshc-smu";
|
|
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x15740000 0x2000>;
|
|
clocks = <&clock_fsys1 ACLK_MMC0>,
|
|
<&clock_top1 CLK_SCLK_MMC0>;
|
|
clock-names = "biu", "ciu";
|
|
fifo-depth = <0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc_1: mmc@15750000 {
|
|
compatible = "samsung,exynos7-dw-mshc";
|
|
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x15750000 0x2000>;
|
|
clocks = <&clock_fsys1 ACLK_MMC1>,
|
|
<&clock_top1 CLK_SCLK_MMC1>;
|
|
clock-names = "biu", "ciu";
|
|
fifo-depth = <0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc_2: mmc@15560000 {
|
|
compatible = "samsung,exynos7-dw-mshc-smu";
|
|
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x15560000 0x2000>;
|
|
clocks = <&clock_fsys0 ACLK_MMC2>,
|
|
<&clock_top1 CLK_SCLK_MMC2>;
|
|
clock-names = "biu", "ciu";
|
|
fifo-depth = <0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
adc: adc@13620000 {
|
|
compatible = "samsung,exynos7-adc";
|
|
reg = <0x13620000 0x100>;
|
|
interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clock_peric0 PCLK_ADCIF>;
|
|
clock-names = "adc";
|
|
#io-channel-cells = <1>;
|
|
io-channel-ranges;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm: pwm@136c0000 {
|
|
compatible = "samsung,exynos4210-pwm";
|
|
reg = <0x136c0000 0x100>;
|
|
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&clock_peric0 PCLK_PWM>;
|
|
clock-names = "timers";
|
|
};
|
|
|
|
tmuctrl_0: tmu@10060000 {
|
|
compatible = "samsung,exynos7-tmu";
|
|
reg = <0x10060000 0x200>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clock_peris PCLK_TMU>,
|
|
<&clock_peris SCLK_TMU>;
|
|
clock-names = "tmu_apbif", "tmu_sclk";
|
|
#include "exynos7-tmu-sensor-conf.dtsi"
|
|
};
|
|
|
|
thermal-zones {
|
|
atlas_thermal: cluster0-thermal {
|
|
polling-delay-passive = <0>; /* milliseconds */
|
|
polling-delay = <0>; /* milliseconds */
|
|
thermal-sensors = <&tmuctrl_0>;
|
|
#include "exynos7-trip-points.dtsi"
|
|
};
|
|
};
|
|
|
|
usbdrd_phy: phy@15500000 {
|
|
compatible = "samsung,exynos7-usbdrd-phy";
|
|
reg = <0x15500000 0x100>;
|
|
clocks = <&clock_fsys0 ACLK_USBDRD300>,
|
|
<&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>,
|
|
<&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,
|
|
<&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>,
|
|
<&clock_fsys0 SCLK_USBDRD300_REFCLK>;
|
|
clock-names = "phy", "ref", "phy_pipe",
|
|
"phy_utmi", "itp";
|
|
samsung,pmu-syscon = <&pmu_system_controller>;
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
usbdrd3 {
|
|
compatible = "samsung,exynos7-dwusb3";
|
|
clocks = <&clock_fsys0 ACLK_USBDRD300>,
|
|
<&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>,
|
|
<&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>;
|
|
clock-names = "usbdrd30", "usbdrd30_susp_clk",
|
|
"usbdrd30_axius_clk";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
dwc3@15400000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x15400000 0x10000>;
|
|
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "exynos7-pinctrl.dtsi"
|