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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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0ee958e102
This patch introduces a new SMP implementation for systems implementing the MIPS Coherent Processing System architecture. The kernel will make use of the Coherence Manager, Cluster Power Controller & Global Interrupt Controller in order to detect, bring up & make use of other cores in the system. SMTC is not supported, so only a single TC per VPE in the system is used. That is, this option enables an SMVP style setup but across multiple cores. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6362/ Patchwork: https://patchwork.linux-mips.org/patch/6611/ Patchwork: https://patchwork.linux-mips.org/patch/6651/ Patchwork: https://patchwork.linux-mips.org/patch/6652/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
34 lines
766 B
C
34 lines
766 B
C
/*
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __MIPS_ASM_SMP_CPS_H__
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#define __MIPS_ASM_SMP_CPS_H__
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#ifndef __ASSEMBLY__
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struct boot_config {
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unsigned int core;
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unsigned int vpe;
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unsigned long pc;
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unsigned long sp;
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unsigned long gp;
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};
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extern struct boot_config mips_cps_bootcfg;
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extern void mips_cps_core_entry(void);
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#else /* __ASSEMBLY__ */
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.extern mips_cps_bootcfg;
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#endif /* __ASSEMBLY__ */
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#endif /* __MIPS_ASM_SMP_CPS_H__ */
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