mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-11 17:56:49 +07:00
6cd94d5e57
New and updated SoC support, notable changes include: * bcm: brcmstb SMP support * bcm: initial iproc/cygnus support * exynos: Exynos4415 SoC support * exynos: PMU and suspend support for Exynos5420 * exynos: PMU support for Exynos3250 * exynos: pm related maintenance * imx: new LS1021A SoC support * imx: vybrid 610 global timer support * integrator: convert to using multiplatform configuration * mediatek: earlyprintk support for mt8127/mt8135 * meson: meson8 soc and l2 cache controller support * mvebu: Armada 38x CPU hotplug support * mvebu: drop support for prerelease Armada 375 Z1 stepping * mvebu: extended suspend support, now works on Armada 370/XP * omap: hwmod related maintenance * omap: prcm cleanup * pxa: initial pxa27x DT handling * rockchip: SMP support for rk3288 * rockchip: add cpu frequency scaling support * shmobile: r8a7740 power domain support * shmobile: various small restart, timer, pci apmu changes * sunxi: Allwinner A80 (sun9i) earlyprintk support * ux500: power domain support Overall, a significant chunk of changes, coming mostly from the usual suspects: omap, shmobile, samsung and mvebu, all of which already contain a lot of platform specific code in arch/arm. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAVIcjyGCrR//JCVInAQJJCRAA1Tm+HZGiAiTvXEAcm/T9tIA08uqtawHt cqyEAUyrnE8QxE4EhUd2pTw4EunVusqKF5EsDxOzw7b3ukUdLAWZE7bqBOSIJLqn hrfsQQ8dXLbyC7T/CHPnBVeM+pn9LiIc9qzpZ0YToiMnHBBI4vKFQntBjd31yoRE hN08I6AmDjQolOzzlqR1fuM0uZaKiHIcytdauTt3Vfqgg7FTHcTy3u1kClHTR1Lp m/KuDothGpR5OKjSnUQz7EO5V3KJEnaKey8z2xM1a7DLLAvJ6r2+DUaDopv9Dbz1 W/V3H7fi5tLvillVa8xmlmzqWZbPc1xw8MWqvHZSWIMRZqloAHpC1VWKn0ZuH4SW 5Bj4ubSrpYjJxjKYfrxtjmuzru3A2jWBNTSP5A4nsny0C3AUsXkfRmRS0VNdegF8 sUdQ1MF8vEMpQT3QPH88+ccFHeIgqbcayhKqLPf7r8q0kwlym5N7Y2amU2A/O6qz +324r+yzfSA70VgJZ5EhXxWVDOPB4Lc8EtoWnH6T/kjncIMwzEsbEbyB3X1OaREW pVn3PNo06VjHLYoiHX+8G99pOFR/JZvaQs6jGCXLs+Orjp5WfP+kafkWqcB5GAKU Pfd3AQsl6rKAITdu0XsTdPiICNS4CmBiWYPepQsTa3pQaNgB7fwZNQKelNRIdGc+ dF1lnQ7CXLQ= =lFoH -----END PGP SIGNATURE----- Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform changes from Arnd Bergmann: "New and updated SoC support, notable changes include: - bcm: brcmstb SMP support initial iproc/cygnus support - exynos: Exynos4415 SoC support PMU and suspend support for Exynos5420 PMU support for Exynos3250 pm related maintenance - imx: new LS1021A SoC support vybrid 610 global timer support - integrator: convert to using multiplatform configuration - mediatek: earlyprintk support for mt8127/mt8135 - meson: meson8 soc and l2 cache controller support - mvebu: Armada 38x CPU hotplug support drop support for prerelease Armada 375 Z1 stepping extended suspend support, now works on Armada 370/XP - omap: hwmod related maintenance prcm cleanup - pxa: initial pxa27x DT handling - rockchip: SMP support for rk3288 add cpu frequency scaling support - shmobile: r8a7740 power domain support various small restart, timer, pci apmu changes - sunxi: Allwinner A80 (sun9i) earlyprintk support - ux500: power domain support Overall, a significant chunk of changes, coming mostly from the usual suspects: omap, shmobile, samsung and mvebu, all of which already contain a lot of platform specific code in arch/arm" * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (187 commits) ARM: mvebu: use the cpufreq-dt platform_data for independent clocks soc: integrator: Add terminating entry for integrator_cm_match ARM: mvebu: add SDRAM controller description for Armada XP ARM: mvebu: adjust mbus controller description on Armada 370/XP ARM: mvebu: add suspend/resume DT information for Armada XP GP ARM: mvebu: synchronize secondary CPU clocks on resume ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume ARM: mvebu: Armada XP GP specific suspend/resume code ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume ARM: mvebu: implement suspend/resume support for Armada XP clk: mvebu: add suspend/resume for gatable clocks bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration bus: mvebu-mbus: suspend/resume support clocksource: time-armada-370-xp: add suspend/resume support irqchip: armada-370-xp: Add suspend/resume support ARM: add lolevel debug support for asm9260 ARM: add mach-asm9260 ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf power: reset: imx-snvs-poweroff: add power off driver for i.mx6 ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A ...
207 lines
5.0 KiB
C
207 lines
5.0 KiB
C
/*
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* R-Car Generation 2 support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Magnus Damm
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* Copyright (C) 2014 Ulrich Hecht
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk/shmobile.h>
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#include <linux/clocksource.h>
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#include <linux/device.h>
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#include <linux/dma-contiguous.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_fdt.h>
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#include <asm/mach/arch.h>
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#include "common.h"
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#include "rcar-gen2.h"
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#define MODEMR 0xe6160060
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u32 rcar_gen2_read_mode_pins(void)
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{
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static u32 mode;
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static bool mode_valid;
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if (!mode_valid) {
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void __iomem *modemr = ioremap_nocache(MODEMR, 4);
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BUG_ON(!modemr);
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mode = ioread32(modemr);
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iounmap(modemr);
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mode_valid = true;
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}
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return mode;
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}
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#define CNTCR 0
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#define CNTFID0 0x20
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void __init rcar_gen2_timer_init(void)
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{
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#if defined(CONFIG_ARM_ARCH_TIMER) || defined(CONFIG_COMMON_CLK)
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u32 mode = rcar_gen2_read_mode_pins();
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bool is_e2 = (bool)of_find_compatible_node(NULL, NULL,
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"renesas,r8a7794");
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#endif
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#ifdef CONFIG_ARM_ARCH_TIMER
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void __iomem *base;
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int extal_mhz = 0;
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u32 freq;
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if (is_e2) {
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freq = 260000000 / 8; /* ZS / 8 */
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/* CNTVOFF has to be initialized either from non-secure
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* Hypervisor mode or secure Monitor mode with SCR.NS==1.
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* If TrustZone is enabled then it should be handled by the
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* secure code.
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*/
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asm volatile(
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" cps 0x16\n"
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" mrc p15, 0, r1, c1, c1, 0\n"
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" orr r0, r1, #1\n"
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" mcr p15, 0, r0, c1, c1, 0\n"
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" isb\n"
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" mov r0, #0\n"
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" mcrr p15, 4, r0, r0, c14\n"
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" isb\n"
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" mcr p15, 0, r1, c1, c1, 0\n"
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" isb\n"
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" cps 0x13\n"
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: : : "r0", "r1");
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} else {
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/* At Linux boot time the r8a7790 arch timer comes up
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* with the counter disabled. Moreover, it may also report
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* a potentially incorrect fixed 13 MHz frequency. To be
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* correct these registers need to be updated to use the
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* frequency EXTAL / 2 which can be determined by the MD pins.
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*/
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switch (mode & (MD(14) | MD(13))) {
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case 0:
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extal_mhz = 15;
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break;
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case MD(13):
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extal_mhz = 20;
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break;
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case MD(14):
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extal_mhz = 26;
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break;
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case MD(13) | MD(14):
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extal_mhz = 30;
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break;
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}
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/* The arch timer frequency equals EXTAL / 2 */
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freq = extal_mhz * (1000000 / 2);
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}
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/* Remap "armgcnt address map" space */
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base = ioremap(0xe6080000, PAGE_SIZE);
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/*
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* Update the timer if it is either not running, or is not at the
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* right frequency. The timer is only configurable in secure mode
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* so this avoids an abort if the loader started the timer and
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* entered the kernel in non-secure mode.
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*/
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if ((ioread32(base + CNTCR) & 1) == 0 ||
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ioread32(base + CNTFID0) != freq) {
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/* Update registers with correct frequency */
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iowrite32(freq, base + CNTFID0);
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asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
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/* make sure arch timer is started by setting bit 0 of CNTCR */
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iowrite32(1, base + CNTCR);
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}
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iounmap(base);
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#endif /* CONFIG_ARM_ARCH_TIMER */
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#ifdef CONFIG_COMMON_CLK
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rcar_gen2_clocks_init(mode);
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#endif
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clocksource_of_init();
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}
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struct memory_reserve_config {
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u64 reserved;
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u64 base, size;
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};
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static int __init rcar_gen2_scan_mem(unsigned long node, const char *uname,
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int depth, void *data)
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{
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const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
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const __be32 *reg, *endp;
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int l;
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struct memory_reserve_config *mrc = data;
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u64 lpae_start = 1ULL << 32;
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/* We are scanning "memory" nodes only */
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if (type == NULL || strcmp(type, "memory"))
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return 0;
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reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l);
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if (reg == NULL)
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reg = of_get_flat_dt_prop(node, "reg", &l);
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if (reg == NULL)
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return 0;
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endp = reg + (l / sizeof(__be32));
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while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) {
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u64 base, size;
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base = dt_mem_next_cell(dt_root_addr_cells, ®);
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size = dt_mem_next_cell(dt_root_size_cells, ®);
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if (base >= lpae_start)
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continue;
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if ((base + size) >= lpae_start)
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size = lpae_start - base;
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if (size < mrc->reserved)
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continue;
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if (base < mrc->base)
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continue;
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/* keep the area at top near the 32-bit legacy limit */
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mrc->base = base + size - mrc->reserved;
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mrc->size = mrc->reserved;
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}
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return 0;
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}
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struct cma *rcar_gen2_dma_contiguous;
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void __init rcar_gen2_reserve(void)
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{
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struct memory_reserve_config mrc;
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/* reserve 256 MiB at the top of the physical legacy 32-bit space */
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memset(&mrc, 0, sizeof(mrc));
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mrc.reserved = SZ_256M;
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of_scan_flat_dt(rcar_gen2_scan_mem, &mrc);
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#ifdef CONFIG_DMA_CMA
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if (mrc.size)
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dma_contiguous_reserve_area(mrc.size, mrc.base, 0,
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&rcar_gen2_dma_contiguous, true);
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#endif
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}
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