Ville Syrjälä 609aeacaac drm/i915: Program VSYNCSHIFT in a more consistent manner ... When interlaced sdvo output is used, vsyncshift should supposedly be (htotal-1)/2. In reality PIPECONF/TRANSCONF will override it by using the legacy vsyncshift interlace mode which causes the hardware to ignore the VSYNCSHIFT register. The only odd thing here is that on PCH platforms we program the VSYNCSHIFT on both CPU and PCH, and it's not entirely clear if both sides have to agree on the value or not. On the CPU side there's no way to override the value via PIPECONF anymore, so if we want to make the CPU side agree with the PCH side, we should probably program the approriate value into VSYNCSHIFT manually. So let's do that, but for now leave the PCH side to still use the legacy interlace mode in TRANSCONF. We can also drop the gen2 check since gen2 doesn't support interlaced modes at all. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2014-03-31 10:46:32 +02:00
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drm	drm/i915: Program VSYNCSHIFT in a more consistent manner	2014-03-31 10:46:32 +02:00
host1x	gpu: host1x: do not check previously handled gathers	2014-02-12 07:50:37 +01:00
vga	vgaarb: Fix VGA decodes changes	2013-09-03 19:17:59 +02:00
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