mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-20 13:30:32 +07:00
ca48b27be7
The Generic Software Interface is a layer of the IPA driver that
abstracts the underlying hardware. The next patch includes the
main code for GSI (including some additional documentation). This
patch just includes three GSI header files.
- "gsi.h" is the top-level GSI header file. This structure is
is embedded within the IPA structure. The main abstraction
implemented by the GSI code is the channel, and this header
exposes several operations that can be performed on a GSI channel.
- "gsi_private.h" exposes some definitions that are intended to be
private, used only by the main GSI code and the GSI transaction
code (defined in an upcoming patch).
- Like "ipa_reg.h", "gsi_reg.h" defines the offsets of the 32-bit
registers used by the GSI layer, along with masks that define the
position and width of fields less than 32 bits located within
these registers.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
418 lines
15 KiB
C
418 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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* Copyright (C) 2018-2020 Linaro Ltd.
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*/
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#ifndef _GSI_REG_H_
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#define _GSI_REG_H_
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/* === Only "gsi.c" should include this file === */
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#include <linux/bits.h>
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/**
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* DOC: GSI Registers
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*
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* GSI registers are located within the "gsi" address space defined by Device
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* Tree. The offset of each register within that space is specified by
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* symbols defined below. The GSI address space is mapped to virtual memory
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* space in gsi_init(). All GSI registers are 32 bits wide.
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*
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* Each register type is duplicated for a number of instances of something.
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* For example, each GSI channel has its own set of registers defining its
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* configuration. The offset to a channel's set of registers is computed
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* based on a "base" offset plus an additional "stride" amount computed
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* from the channel's ID. For such registers, the offset is computed by a
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* function-like macro that takes a parameter used in the computation.
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*
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* The offset of a register dependent on execution environment is computed
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* by a macro that is supplied a parameter "ee". The "ee" value is a member
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* of the gsi_ee_id enumerated type.
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*
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* The offset of a channel register is computed by a macro that is supplied a
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* parameter "ch". The "ch" value is a channel id whose maximum value is 30
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* (though the actual limit is hardware-dependent).
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*
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* The offset of an event register is computed by a macro that is supplied a
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* parameter "ev". The "ev" value is an event id whose maximum value is 15
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* (though the actual limit is hardware-dependent).
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*/
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#define GSI_INTER_EE_SRC_CH_IRQ_OFFSET \
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GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(GSI_EE_AP)
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#define GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(ee) \
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(0x0000c018 + 0x1000 * (ee))
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#define GSI_INTER_EE_SRC_EV_CH_IRQ_OFFSET \
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GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP)
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#define GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(ee) \
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(0x0000c01c + 0x1000 * (ee))
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#define GSI_INTER_EE_SRC_CH_IRQ_CLR_OFFSET \
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GSI_INTER_EE_N_SRC_CH_IRQ_CLR_OFFSET(GSI_EE_AP)
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#define GSI_INTER_EE_N_SRC_CH_IRQ_CLR_OFFSET(ee) \
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(0x0000c028 + 0x1000 * (ee))
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#define GSI_INTER_EE_SRC_EV_CH_IRQ_CLR_OFFSET \
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GSI_INTER_EE_N_SRC_EV_CH_IRQ_CLR_OFFSET(GSI_EE_AP)
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#define GSI_INTER_EE_N_SRC_EV_CH_IRQ_CLR_OFFSET(ee) \
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(0x0000c02c + 0x1000 * (ee))
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#define GSI_CH_C_CNTXT_0_OFFSET(ch) \
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GSI_EE_N_CH_C_CNTXT_0_OFFSET((ch), GSI_EE_AP)
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#define GSI_EE_N_CH_C_CNTXT_0_OFFSET(ch, ee) \
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(0x0001c000 + 0x4000 * (ee) + 0x80 * (ch))
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#define CHTYPE_PROTOCOL_FMASK GENMASK(2, 0)
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#define CHTYPE_DIR_FMASK GENMASK(3, 3)
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#define EE_FMASK GENMASK(7, 4)
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#define CHID_FMASK GENMASK(12, 8)
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/* The next field is present for GSI v2.0 and above */
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#define CHTYPE_PROTOCOL_MSB_FMASK GENMASK(13, 13)
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#define ERINDEX_FMASK GENMASK(18, 14)
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#define CHSTATE_FMASK GENMASK(23, 20)
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#define ELEMENT_SIZE_FMASK GENMASK(31, 24)
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#define GSI_CH_C_CNTXT_1_OFFSET(ch) \
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GSI_EE_N_CH_C_CNTXT_1_OFFSET((ch), GSI_EE_AP)
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#define GSI_EE_N_CH_C_CNTXT_1_OFFSET(ch, ee) \
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(0x0001c004 + 0x4000 * (ee) + 0x80 * (ch))
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#define R_LENGTH_FMASK GENMASK(15, 0)
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#define GSI_CH_C_CNTXT_2_OFFSET(ch) \
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GSI_EE_N_CH_C_CNTXT_2_OFFSET((ch), GSI_EE_AP)
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#define GSI_EE_N_CH_C_CNTXT_2_OFFSET(ch, ee) \
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(0x0001c008 + 0x4000 * (ee) + 0x80 * (ch))
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#define GSI_CH_C_CNTXT_3_OFFSET(ch) \
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GSI_EE_N_CH_C_CNTXT_3_OFFSET((ch), GSI_EE_AP)
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#define GSI_EE_N_CH_C_CNTXT_3_OFFSET(ch, ee) \
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(0x0001c00c + 0x4000 * (ee) + 0x80 * (ch))
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#define GSI_CH_C_QOS_OFFSET(ch) \
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GSI_EE_N_CH_C_QOS_OFFSET((ch), GSI_EE_AP)
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#define GSI_EE_N_CH_C_QOS_OFFSET(ch, ee) \
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(0x0001c05c + 0x4000 * (ee) + 0x80 * (ch))
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#define WRR_WEIGHT_FMASK GENMASK(3, 0)
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#define MAX_PREFETCH_FMASK GENMASK(8, 8)
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#define USE_DB_ENG_FMASK GENMASK(9, 9)
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/* The next field is present for GSI v2.0 and above */
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#define USE_ESCAPE_BUF_ONLY_FMASK GENMASK(10, 10)
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#define GSI_CH_C_SCRATCH_0_OFFSET(ch) \
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GSI_EE_N_CH_C_SCRATCH_0_OFFSET((ch), GSI_EE_AP)
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#define GSI_EE_N_CH_C_SCRATCH_0_OFFSET(ch, ee) \
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(0x0001c060 + 0x4000 * (ee) + 0x80 * (ch))
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#define GSI_CH_C_SCRATCH_1_OFFSET(ch) \
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GSI_EE_N_CH_C_SCRATCH_1_OFFSET((ch), GSI_EE_AP)
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#define GSI_EE_N_CH_C_SCRATCH_1_OFFSET(ch, ee) \
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(0x0001c064 + 0x4000 * (ee) + 0x80 * (ch))
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#define GSI_CH_C_SCRATCH_2_OFFSET(ch) \
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GSI_EE_N_CH_C_SCRATCH_2_OFFSET((ch), GSI_EE_AP)
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#define GSI_EE_N_CH_C_SCRATCH_2_OFFSET(ch, ee) \
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(0x0001c068 + 0x4000 * (ee) + 0x80 * (ch))
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#define GSI_CH_C_SCRATCH_3_OFFSET(ch) \
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GSI_EE_N_CH_C_SCRATCH_3_OFFSET((ch), GSI_EE_AP)
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#define GSI_EE_N_CH_C_SCRATCH_3_OFFSET(ch, ee) \
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(0x0001c06c + 0x4000 * (ee) + 0x80 * (ch))
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#define GSI_EV_CH_E_CNTXT_0_OFFSET(ev) \
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GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET((ev), GSI_EE_AP)
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#define GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET(ev, ee) \
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(0x0001d000 + 0x4000 * (ee) + 0x80 * (ev))
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#define EV_CHTYPE_FMASK GENMASK(3, 0)
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#define EV_EE_FMASK GENMASK(7, 4)
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#define EV_EVCHID_FMASK GENMASK(15, 8)
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#define EV_INTYPE_FMASK GENMASK(16, 16)
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#define EV_CHSTATE_FMASK GENMASK(23, 20)
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#define EV_ELEMENT_SIZE_FMASK GENMASK(31, 24)
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#define GSI_EV_CH_E_CNTXT_1_OFFSET(ev) \
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GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET((ev), GSI_EE_AP)
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#define GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET(ev, ee) \
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(0x0001d004 + 0x4000 * (ee) + 0x80 * (ev))
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#define EV_R_LENGTH_FMASK GENMASK(15, 0)
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#define GSI_EV_CH_E_CNTXT_2_OFFSET(ev) \
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GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET((ev), GSI_EE_AP)
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#define GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET(ev, ee) \
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(0x0001d008 + 0x4000 * (ee) + 0x80 * (ev))
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#define GSI_EV_CH_E_CNTXT_3_OFFSET(ev) \
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GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET((ev), GSI_EE_AP)
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#define GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET(ev, ee) \
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(0x0001d00c + 0x4000 * (ee) + 0x80 * (ev))
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#define GSI_EV_CH_E_CNTXT_4_OFFSET(ev) \
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GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET((ev), GSI_EE_AP)
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#define GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET(ev, ee) \
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(0x0001d010 + 0x4000 * (ee) + 0x80 * (ev))
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#define GSI_EV_CH_E_CNTXT_8_OFFSET(ev) \
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GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET((ev), GSI_EE_AP)
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#define GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET(ev, ee) \
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(0x0001d020 + 0x4000 * (ee) + 0x80 * (ev))
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#define MODT_FMASK GENMASK(15, 0)
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#define MODC_FMASK GENMASK(23, 16)
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#define MOD_CNT_FMASK GENMASK(31, 24)
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#define GSI_EV_CH_E_CNTXT_9_OFFSET(ev) \
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GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET((ev), GSI_EE_AP)
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#define GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET(ev, ee) \
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(0x0001d024 + 0x4000 * (ee) + 0x80 * (ev))
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#define GSI_EV_CH_E_CNTXT_10_OFFSET(ev) \
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GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET((ev), GSI_EE_AP)
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#define GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET(ev, ee) \
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(0x0001d028 + 0x4000 * (ee) + 0x80 * (ev))
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#define GSI_EV_CH_E_CNTXT_11_OFFSET(ev) \
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GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET((ev), GSI_EE_AP)
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#define GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET(ev, ee) \
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(0x0001d02c + 0x4000 * (ee) + 0x80 * (ev))
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#define GSI_EV_CH_E_CNTXT_12_OFFSET(ev) \
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GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET((ev), GSI_EE_AP)
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#define GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET(ev, ee) \
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(0x0001d030 + 0x4000 * (ee) + 0x80 * (ev))
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#define GSI_EV_CH_E_CNTXT_13_OFFSET(ev) \
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GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET((ev), GSI_EE_AP)
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#define GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET(ev, ee) \
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(0x0001d034 + 0x4000 * (ee) + 0x80 * (ev))
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#define GSI_EV_CH_E_SCRATCH_0_OFFSET(ev) \
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GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET((ev), GSI_EE_AP)
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#define GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET(ev, ee) \
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(0x0001d048 + 0x4000 * (ee) + 0x80 * (ev))
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#define GSI_EV_CH_E_SCRATCH_1_OFFSET(ev) \
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GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET((ev), GSI_EE_AP)
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#define GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET(ev, ee) \
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(0x0001d04c + 0x4000 * (ee) + 0x80 * (ev))
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#define GSI_CH_C_DOORBELL_0_OFFSET(ch) \
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GSI_EE_N_CH_C_DOORBELL_0_OFFSET((ch), GSI_EE_AP)
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#define GSI_EE_N_CH_C_DOORBELL_0_OFFSET(ch, ee) \
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(0x0001e000 + 0x4000 * (ee) + 0x08 * (ch))
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#define GSI_EV_CH_E_DOORBELL_0_OFFSET(ev) \
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GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET((ev), GSI_EE_AP)
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#define GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET(ev, ee) \
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(0x0001e100 + 0x4000 * (ee) + 0x08 * (ev))
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#define GSI_GSI_STATUS_OFFSET \
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GSI_EE_N_GSI_STATUS_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_GSI_STATUS_OFFSET(ee) \
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(0x0001f000 + 0x4000 * (ee))
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#define ENABLED_FMASK GENMASK(0, 0)
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#define GSI_CH_CMD_OFFSET \
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GSI_EE_N_CH_CMD_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_CH_CMD_OFFSET(ee) \
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(0x0001f008 + 0x4000 * (ee))
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#define CH_CHID_FMASK GENMASK(7, 0)
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#define CH_OPCODE_FMASK GENMASK(31, 24)
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#define GSI_EV_CH_CMD_OFFSET \
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GSI_EE_N_EV_CH_CMD_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_EV_CH_CMD_OFFSET(ee) \
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(0x0001f010 + 0x4000 * (ee))
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#define EV_CHID_FMASK GENMASK(7, 0)
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#define EV_OPCODE_FMASK GENMASK(31, 24)
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#define GSI_GENERIC_CMD_OFFSET \
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GSI_EE_N_GENERIC_CMD_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_GENERIC_CMD_OFFSET(ee) \
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(0x0001f018 + 0x4000 * (ee))
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#define GENERIC_OPCODE_FMASK GENMASK(4, 0)
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#define GENERIC_CHID_FMASK GENMASK(9, 5)
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#define GENERIC_EE_FMASK GENMASK(13, 10)
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#define GSI_GSI_HW_PARAM_2_OFFSET \
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GSI_EE_N_GSI_HW_PARAM_2_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_GSI_HW_PARAM_2_OFFSET(ee) \
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(0x0001f040 + 0x4000 * (ee))
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#define IRAM_SIZE_FMASK GENMASK(2, 0)
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#define IRAM_SIZE_ONE_KB_FVAL 0
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#define IRAM_SIZE_TWO_KB_FVAL 1
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/* The next two values are available for GSI v2.0 and above */
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#define IRAM_SIZE_TWO_N_HALF_KB_FVAL 2
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#define IRAM_SIZE_THREE_KB_FVAL 3
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#define NUM_CH_PER_EE_FMASK GENMASK(7, 3)
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#define NUM_EV_PER_EE_FMASK GENMASK(12, 8)
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#define GSI_CH_PEND_TRANSLATE_FMASK GENMASK(13, 13)
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#define GSI_CH_FULL_LOGIC_FMASK GENMASK(14, 14)
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/* Fields below are present for GSI v2.0 and above */
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#define GSI_USE_SDMA_FMASK GENMASK(15, 15)
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#define GSI_SDMA_N_INT_FMASK GENMASK(18, 16)
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#define GSI_SDMA_MAX_BURST_FMASK GENMASK(26, 19)
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#define GSI_SDMA_N_IOVEC_FMASK GENMASK(29, 27)
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/* Fields below are present for GSI v2.2 and above */
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#define GSI_USE_RD_WR_ENG_FMASK GENMASK(30, 30)
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#define GSI_USE_INTER_EE_FMASK GENMASK(31, 31)
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#define GSI_CNTXT_TYPE_IRQ_OFFSET \
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GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(ee) \
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(0x0001f080 + 0x4000 * (ee))
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#define CH_CTRL_FMASK GENMASK(0, 0)
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#define EV_CTRL_FMASK GENMASK(1, 1)
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#define GLOB_EE_FMASK GENMASK(2, 2)
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#define IEOB_FMASK GENMASK(3, 3)
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#define INTER_EE_CH_CTRL_FMASK GENMASK(4, 4)
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#define INTER_EE_EV_CTRL_FMASK GENMASK(5, 5)
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#define GENERAL_FMASK GENMASK(6, 6)
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#define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \
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GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \
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(0x0001f088 + 0x4000 * (ee))
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#define MSK_CH_CTRL_FMASK GENMASK(0, 0)
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#define MSK_EV_CTRL_FMASK GENMASK(1, 1)
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#define MSK_GLOB_EE_FMASK GENMASK(2, 2)
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#define MSK_IEOB_FMASK GENMASK(3, 3)
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#define MSK_INTER_EE_CH_CTRL_FMASK GENMASK(4, 4)
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#define MSK_INTER_EE_EV_CTRL_FMASK GENMASK(5, 5)
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#define MSK_GENERAL_FMASK GENMASK(6, 6)
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#define GSI_CNTXT_TYPE_IRQ_MSK_ALL GENMASK(6, 0)
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#define GSI_CNTXT_SRC_CH_IRQ_OFFSET \
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GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(ee) \
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(0x0001f090 + 0x4000 * (ee))
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#define GSI_CNTXT_SRC_EV_CH_IRQ_OFFSET \
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GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(ee) \
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(0x0001f094 + 0x4000 * (ee))
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#define GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET \
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GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(ee) \
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(0x0001f098 + 0x4000 * (ee))
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#define GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET \
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GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(ee) \
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(0x0001f09c + 0x4000 * (ee))
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#define GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET \
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GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(ee) \
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(0x0001f0a0 + 0x4000 * (ee))
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#define GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET \
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GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(ee) \
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(0x0001f0a4 + 0x4000 * (ee))
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#define GSI_CNTXT_SRC_IEOB_IRQ_OFFSET \
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GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(ee) \
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(0x0001f0b0 + 0x4000 * (ee))
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#define GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET \
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GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(ee) \
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(0x0001f0b8 + 0x4000 * (ee))
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#define GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET \
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GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(ee) \
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(0x0001f0c0 + 0x4000 * (ee))
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#define GSI_CNTXT_GLOB_IRQ_STTS_OFFSET \
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GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(ee) \
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(0x0001f100 + 0x4000 * (ee))
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#define ERROR_INT_FMASK GENMASK(0, 0)
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#define GP_INT1_FMASK GENMASK(1, 1)
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#define GP_INT2_FMASK GENMASK(2, 2)
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#define GP_INT3_FMASK GENMASK(3, 3)
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#define GSI_CNTXT_GLOB_IRQ_EN_OFFSET \
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GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(ee) \
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(0x0001f108 + 0x4000 * (ee))
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#define EN_ERROR_INT_FMASK GENMASK(0, 0)
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#define EN_GP_INT1_FMASK GENMASK(1, 1)
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#define EN_GP_INT2_FMASK GENMASK(2, 2)
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#define EN_GP_INT3_FMASK GENMASK(3, 3)
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#define GSI_CNTXT_GLOB_IRQ_ALL GENMASK(3, 0)
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#define GSI_CNTXT_GLOB_IRQ_CLR_OFFSET \
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GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(ee) \
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(0x0001f110 + 0x4000 * (ee))
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#define CLR_ERROR_INT_FMASK GENMASK(0, 0)
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#define CLR_GP_INT1_FMASK GENMASK(1, 1)
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#define CLR_GP_INT2_FMASK GENMASK(2, 2)
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#define CLR_GP_INT3_FMASK GENMASK(3, 3)
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#define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \
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GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(ee) \
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(0x0001f118 + 0x4000 * (ee))
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#define BREAK_POINT_FMASK GENMASK(0, 0)
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#define BUS_ERROR_FMASK GENMASK(1, 1)
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#define CMD_FIFO_OVRFLOW_FMASK GENMASK(2, 2)
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#define MCS_STACK_OVRFLOW_FMASK GENMASK(3, 3)
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#define GSI_CNTXT_GSI_IRQ_EN_OFFSET \
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GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(ee) \
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(0x0001f120 + 0x4000 * (ee))
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#define EN_BREAK_POINT_FMASK GENMASK(0, 0)
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#define EN_BUS_ERROR_FMASK GENMASK(1, 1)
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#define EN_CMD_FIFO_OVRFLOW_FMASK GENMASK(2, 2)
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#define EN_MCS_STACK_OVRFLOW_FMASK GENMASK(3, 3)
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#define GSI_CNTXT_GSI_IRQ_ALL GENMASK(3, 0)
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#define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \
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GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(ee) \
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(0x0001f128 + 0x4000 * (ee))
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#define CLR_BREAK_POINT_FMASK GENMASK(0, 0)
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#define CLR_BUS_ERROR_FMASK GENMASK(1, 1)
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#define CLR_CMD_FIFO_OVRFLOW_FMASK GENMASK(2, 2)
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#define CLR_MCS_STACK_OVRFLOW_FMASK GENMASK(3, 3)
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#define GSI_CNTXT_INTSET_OFFSET \
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GSI_EE_N_CNTXT_INTSET_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_CNTXT_INTSET_OFFSET(ee) \
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(0x0001f180 + 0x4000 * (ee))
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#define INTYPE_FMASK GENMASK(0, 0)
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#define GSI_ERROR_LOG_OFFSET \
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GSI_EE_N_ERROR_LOG_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_ERROR_LOG_OFFSET(ee) \
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(0x0001f200 + 0x4000 * (ee))
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#define ERR_ARG3_FMASK GENMASK(3, 0)
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#define ERR_ARG2_FMASK GENMASK(7, 4)
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#define ERR_ARG1_FMASK GENMASK(11, 8)
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#define ERR_CODE_FMASK GENMASK(15, 12)
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#define ERR_VIRT_IDX_FMASK GENMASK(23, 19)
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#define ERR_TYPE_FMASK GENMASK(27, 24)
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#define ERR_EE_FMASK GENMASK(31, 28)
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#define GSI_ERROR_LOG_CLR_OFFSET \
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GSI_EE_N_ERROR_LOG_CLR_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_ERROR_LOG_CLR_OFFSET(ee) \
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(0x0001f210 + 0x4000 * (ee))
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#define GSI_CNTXT_SCRATCH_0_OFFSET \
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GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(GSI_EE_AP)
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#define GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(ee) \
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(0x0001f400 + 0x4000 * (ee))
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#define INTER_EE_RESULT_FMASK GENMASK(2, 0)
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#define GENERIC_EE_RESULT_FMASK GENMASK(7, 5)
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#define GENERIC_EE_SUCCESS_FVAL 1
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#define GENERIC_EE_NO_RESOURCES_FVAL 7
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#define USB_MAX_PACKET_FMASK GENMASK(15, 15) /* 0: HS; 1: SS */
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#define MHI_BASE_CHANNEL_FMASK GENMASK(31, 24)
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#endif /* _GSI_REG_H_ */
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