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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1ea4b76cdf
Add support for i.MX6UL modules from Kontron Electronics GmbH (before acquisition: Exceet Electronics) and evalkit boards based on it: 1. N6310 SOM: i.MX6 UL System-on-Module, a 25x25 mm solderable module (LGA pads and pin castellations) with 256 MB RAM, 1 MB NOR-Flash, 256 MB NAND and other interfaces, 2. N6310 S: evalkit, w/wo eMMC, without display, 3. N6310 S 43: evalkit with 4.3" display, The work is based on Exceet/Kontron source code (GPLv2) with numerous changes: 1. Reorganize files, 2. Rename Exceet -> Kontron, 3. Rename models/compatibles to match newest Kontron product naming, 4. Fix coding style errors and adjust to device tree coding guidelines, 5. Fix DTC warnings, 6. Extend compatibles so eval boards inherit the SoM compatible, 7. Use defines instead of GPIO and interrupt flag values, 8. Use proper vendor compatible for Macronix SPI NOR, 9. Replace deprecated bindings with proper ones, 10. Sort nodes alphabetically, 11. Remove Admatec display nodes (not yet supported). Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
135 lines
2.9 KiB
Plaintext
135 lines
2.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2017 exceet electronics GmbH
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* Copyright (C) 2018 Kontron Electronics GmbH
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* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
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*/
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#include "imx6ul.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Kontron N6310 SOM";
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compatible = "kontron,imx6ul-n6310-som", "fsl,imx6ul";
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memory@80000000 {
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reg = <0x80000000 0x10000000>;
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device_type = "memory";
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};
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};
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&ecspi2 {
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cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi2>;
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status = "okay";
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spi-flash@0 {
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compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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reg = <0>;
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
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phy-mode = "rmii";
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phy-handle = <ðphy1>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy1: ethernet-phy@1 {
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reg = <1>;
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micrel,led-mode = <0>;
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clocks = <&clks IMX6UL_CLK_ENET_REF>;
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clock-names = "rmii-ref";
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};
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};
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};
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&fec2 {
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phy-mode = "rmii";
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status = "disabled";
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};
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&qspi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi>;
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-nand";
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spi-max-frequency = <108000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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reg = <0>;
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partition@0 {
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label = "ubi1";
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reg = <0x00000000 0x08000000>;
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};
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partition@8000000 {
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label = "ubi2";
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reg = <0x08000000 0x08000000>;
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};
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reset_out>;
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pinctrl_ecspi2: ecspi2grp {
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fsl,pins = <
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MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1
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MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1
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MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1
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MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1
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>;
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};
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009
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>;
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};
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pinctrl_enet1_mdio: enet1mdiogrp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
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MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
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>;
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};
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pinctrl_qspi: qspigrp {
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fsl,pins = <
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MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
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MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
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MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
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MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
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MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
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MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
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>;
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};
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pinctrl_reset_out: rstoutgrp {
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fsl,pins = <
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MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
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>;
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};
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};
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