mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 22:59:08 +07:00
b2cc26af46
The change to include ibm-power9-cfam.dtsi resulted in a renumbering of all of the I2C bus numbers behind the on-board muxes. This breaks some tools which have hardcoded the bus numbers. Add device tree aliases for the I2C buses routed through the PCIe slots so that they return to their former numbers before the cfam change. Signed-off-by: Robert Lippert <rlippert@google.com> Signed-off-by: Patrick Venture <venture@google.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
545 lines
8.8 KiB
Plaintext
545 lines
8.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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#include "aspeed-g5.dtsi"
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#include <dt-bindings/gpio/aspeed-gpio.h>
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/ {
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model = "Zaius BMC";
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compatible = "ingrasys,zaius-bmc", "aspeed,ast2500";
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aliases {
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i2c15 = &i2cpcie0;
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i2c16 = &i2cpcie1;
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i2c17 = &i2cpcie2;
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i2c19 = &i2cpcie3;
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i2c20 = &i2cpcie4;
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};
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chosen {
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stdout-path = &uart5;
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bootargs = "console=ttyS4,115200 earlyprintk";
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};
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memory@80000000 {
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reg = <0x80000000 0x40000000>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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flash_memory: region@98000000 {
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no-map;
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reg = <0x98000000 0x04000000>; /* 64M */
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};
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};
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onewire0 {
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compatible = "w1-gpio";
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gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
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};
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onewire1 {
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compatible = "w1-gpio";
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gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
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};
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onewire2 {
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compatible = "w1-gpio";
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gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
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};
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onewire3 {
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compatible = "w1-gpio";
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gpios = <&gpio ASPEED_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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checkstop {
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label = "checkstop";
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gpios = <&gpio ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>;
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linux,code = <ASPEED_GPIO(F, 7)>;
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};
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pcie-e2b-present{
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label = "pcie-e2b-present";
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gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>;
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linux,code = <ASPEED_GPIO(E, 7)>;
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};
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};
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leds {
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compatible = "gpio-leds";
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sys_boot_status {
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label = "System boot status";
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gpios = <&gpio ASPEED_GPIO(D, 5) GPIO_ACTIVE_LOW>;
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};
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attention {
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label = "Attention";
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gpios = <&gpio ASPEED_GPIO(D, 6) GPIO_ACTIVE_LOW>;
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};
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plt_fault {
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label = "Platform fault";
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gpios = <&gpio ASPEED_GPIO(D, 7) GPIO_ACTIVE_LOW>;
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};
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hdd_fault {
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label = "Onboard drive fault";
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gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>;
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};
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};
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fsi: gpio-fsi {
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compatible = "fsi-master-gpio", "fsi-master";
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#address-cells = <2>;
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#size-cells = <0>;
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no-gpio-delays;
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trans-gpios = <&gpio ASPEED_GPIO(O, 6) GPIO_ACTIVE_HIGH>;
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enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
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clock-gpios = <&gpio ASPEED_GPIO(G, 0) GPIO_ACTIVE_HIGH>;
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data-gpios = <&gpio ASPEED_GPIO(G, 1) GPIO_ACTIVE_HIGH>;
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mux-gpios = <&gpio ASPEED_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
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};
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iio-hwmon {
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compatible = "iio-hwmon";
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io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
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<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
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<&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>,
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<&adc 13>, <&adc 14>, <&adc 15>;
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};
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iio-hwmon-battery {
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compatible = "iio-hwmon";
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io-channels = <&adc 12>;
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};
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};
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&fmc {
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status = "okay";
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flash@0 {
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status = "okay";
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label = "bmc";
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m25p,fast-read;
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#include "openbmc-flash-layout.dtsi"
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};
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};
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&spi1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi1_default>;
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flash@0 {
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status = "okay";
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label = "pnor";
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m25p,fast-read;
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};
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};
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&spi2 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi2ck_default
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&pinctrl_spi2cs0_default
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&pinctrl_spi2cs1_default
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&pinctrl_spi2miso_default
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&pinctrl_spi2mosi_default>;
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flash@0 {
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status = "okay";
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};
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_txd1_default
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&pinctrl_rxd1_default>;
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};
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&lpc_ctrl {
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status = "okay";
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memory-region = <&flash_memory>;
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flash = <&spi1>;
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};
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&lpc_snoop {
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status = "okay";
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snoop-ports = <0x80>;
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};
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&uart5 {
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status = "okay";
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};
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&mac0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rmii1_default>;
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use-ncsi;
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};
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&mac1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
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};
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&i2c0 {
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status = "okay";
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eeprom@50 {
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compatible = "atmel,24c64";
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reg = <0x50>;
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pagesize = <32>;
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};
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rtc@68 {
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compatible = "nxp,pcf8523";
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reg = <0x68>;
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};
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ucd90160@64 {
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compatible = "ti,ucd90160";
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reg = <0x64>;
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};
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/* Power sequencer UCD90160 PMBUS @64h
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* FRU AT24C64D @50h
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* RTC PCF8523 @68h
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* Clock buffer 9DBL04 @6dh
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*/
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};
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&i2c1 {
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status = "okay";
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i2c-switch@71 {
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compatible = "nxp,pca9546";
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reg = <0x71>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2cpcie0: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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i2cpcie1: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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i2cpcie2: i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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};
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i2ctpm: i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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};
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};
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/* MUX1 PCA9546A @71h
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* PCIe 0
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* PCIe 1
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* PCIe 2
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* TPM header
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*/
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};
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&i2c2 {
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status = "disabled";
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/* OCP Mezz Connector A (OOB SMBUS) */
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};
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&i2c3 {
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status = "disabled";
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/* OCP Mezz Connector A (PCIe slot SMBUS) */
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};
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&i2c4 {
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status = "okay";
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i2c-switch@71 {
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compatible = "nxp,pca9546";
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reg = <0x71>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2cpcie3: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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i2cpcie4: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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};
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/* MUX1 PCA9546A @71h
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* PCIe 3
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* PCIe 4
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*/
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};
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&i2c5 {
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status = "disabled";
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/* CPU0 PRM 0.7V */
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/* CPU0 PRM 1.2V CH03 */
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/* CPU0 PRM 0.8V */
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/* CPU0 PRM 1.2V CH47 */
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};
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&i2c6 {
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status = "disabled";
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/* CPU1 PRM 0.7V */
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/* CPU1 PRM 1.2V CH03 */
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/* CPU1 PRM 0.8V */
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/* CPU1 PRM 1.2V CH47 */
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};
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&i2c7 {
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status = "okay";
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pca9541a@70 {
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compatible = "nxp,pca9541";
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reg = <0x70>;
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i2c-arb {
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#address-cells = <1>;
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#size-cells = <0>;
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hotswap@54 {
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compatible = "ti,lm5066i";
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reg = <0x54>;
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};
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};
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};
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vrm@64 {
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compatible = "isil,isl68137";
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reg = <0x64>;
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};
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vrm@40 {
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compatible = "isil,isl68137";
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reg = <0x40>;
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};
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vrm@60 {
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compatible = "isil,isl68137";
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reg = <0x60>;
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};
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vrm@43 {
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compatible = "infineon,ir38064";
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reg = <0x43>;
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};
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vrm@41 {
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compatible = "isil,isl68137";
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reg = <0x41>;
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};
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/* Master selector PCA9541A @70h (other master: CPU0)
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* LM5066I PMBUS @10h
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*/
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/*
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* Brick will be one of these types/addresses. Depending
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* on the board SKU only one is actually present and will successfully
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* instantiate while the others will fail the probe operation.
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* These are the PVT (and presumably beyond) addresses:
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* 12V Quarter Brick DC/DC Converter Q54SJ12050 @6Ah
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* 12V Quarter Brick DC/DC Converter Q54SH12050 @30h
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*/
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power-brick@6a {
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compatible = "delta,dps800";
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reg = <0x6a>;
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};
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power-brick@30 {
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compatible = "delta,dps800";
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reg = <0x30>;
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};
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/* CPU0 VR ISL68137 0.7V, 0.96V PMBUS @64h */
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/* CPU0 VR ISL68137 1.2V CH03 PMBUS @40h */
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/* CPU0 VR ISL68137 0.8V PMBUS @60h */
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/* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @43h */
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/* CPU0 VR ISL68137 1.2V CH47 PMBUS @41h */
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/* Master selector PCA9541A @70h (other master: CPU0)
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* LM5066I PMBUS @10h
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*/
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};
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&i2c8 {
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status = "okay";
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vrm@64 {
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compatible = "isil,isl68137";
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reg = <0x64>;
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};
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vrm@40 {
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compatible = "isil,isl68137";
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reg = <0x40>;
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};
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vrm@41 {
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compatible = "isil,isl68137";
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reg = <0x41>;
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};
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vrm@42 {
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compatible = "infineon,ir38064";
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reg = <0x42>;
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};
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vrm@60 {
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compatible = "isil,isl68137";
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reg = <0x60>;
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};
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/* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @64h */
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/* CPU1 VR ISL68137 1.2V CH03 PMBUS @40h */
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/* CPU1 VR ISL68137 1.2V CH47 PMBUS @41h */
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/* CPU1 VR 1.0V IR38064 I2C @12h, PMBUS @42h */
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/* CPU1 VR ISL68137 0.8V PMBUS @60h */
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};
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&i2c9 {
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status = "disabled";
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/* Fan board */
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};
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&i2c10 {
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status = "disabled";
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};
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&i2c11 {
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status = "disabled";
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/* GPU sideband */
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};
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&i2c12 {
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status = "disabled";
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};
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&i2c13 {
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status = "disabled";
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/* MUX PI3USB102
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* CPU0 debug
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* CPU1 debug
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*/
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};
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&pinctrl {
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aspeed,external-nodes = <&gfx &lhc>;
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pinctrl_gpioh_unbiased: gpioi_unbiased {
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pins = "A8", "C7", "B7", "A7", "D7", "B6", "A6", "E7";
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bias-disable;
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};
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};
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&gpio {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpioh_unbiased>;
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line_iso_u146_en {
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gpio-hog;
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gpios = <ASPEED_GPIO(O, 4) GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "iso_u164_en";
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};
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ncsi_mux_en_n {
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gpio-hog;
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gpios = <ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "ncsi_mux_en_n";
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};
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line_bmc_i2c2_sw_rst_n {
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gpio-hog;
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gpios = <ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "bmc_i2c2_sw_rst_n";
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};
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line_bmc_i2c5_sw_rst_n {
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gpio-hog;
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gpios = <ASPEED_GPIO(P, 3) GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "bmc_i2c5_sw_rst_n";
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};
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};
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&vuart {
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status = "okay";
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};
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&gfx {
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status = "okay";
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};
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&pwm_tacho {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
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&pinctrl_pwm2_default &pinctrl_pwm3_default>;
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fan@0 {
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reg = <0x00>;
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aspeed,fan-tach-ch = /bits/ 8 <0x00>;
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};
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fan@1 {
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reg = <0x01>;
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aspeed,fan-tach-ch = /bits/ 8 <0x01>;
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};
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fan@2 {
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reg = <0x02>;
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aspeed,fan-tach-ch = /bits/ 8 <0x02>;
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};
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fan@3 {
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reg = <0x03>;
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aspeed,fan-tach-ch = /bits/ 8 <0x03>;
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};
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};
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&ibt {
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status = "okay";
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};
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#include "ibm-power9-dual.dtsi"
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