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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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861c056953
Add the SYS block registers for XLP9XX, most of them have changed. The wakeup sequence has been updated to set the coherent mode from the main thread rather than the woken up thread. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6280/
261 lines
6.7 KiB
ArmAsm
261 lines
6.7 KiB
ArmAsm
/*
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* Copyright 2003-2013 Broadcom Corporation.
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* All Rights Reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the Broadcom
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/init.h>
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#include <asm/asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/cacheops.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/stackframe.h>
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#include <asm/asmmacro.h>
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#include <asm/addrspace.h>
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#include <asm/netlogic/common.h>
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/sys.h>
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#include <asm/netlogic/xlp-hal/cpucontrol.h>
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#define CP0_EBASE $15
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#define SYS_CPU_COHERENT_BASE CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
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XLP_IO_SYS_OFFSET(0) + XLP_IO_PCI_HDRSZ + \
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SYS_CPU_NONCOHERENT_MODE * 4
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/* Enable XLP features and workarounds in the LSU */
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.macro xlp_config_lsu
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li t0, LSU_DEFEATURE
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mfcr t1, t0
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lui t2, 0xc080 /* SUE, Enable Unaligned Access, L2HPE */
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or t1, t1, t2
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mtcr t1, t0
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li t0, ICU_DEFEATURE
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mfcr t1, t0
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ori t1, 0x1000 /* Enable Icache partitioning */
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mtcr t1, t0
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li t0, SCHED_DEFEATURE
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lui t1, 0x0100 /* Disable BRU accepting ALU ops */
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mtcr t1, t0
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.endm
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/*
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* L1D cache has to be flushed before enabling threads in XLP.
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* On XLP8xx/XLP3xx, we do a low level flush using processor control
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* registers. On XLPII CPUs, usual cache instructions work.
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*/
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.macro xlp_flush_l1_dcache
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mfc0 t0, CP0_EBASE, 0
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andi t0, t0, 0xff00
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slt t1, t0, 0x1200
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beqz t1, 15f
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nop
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/* XLP8xx low level cache flush */
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li t0, LSU_DEBUG_DATA0
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li t1, LSU_DEBUG_ADDR
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li t2, 0 /* index */
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li t3, 0x1000 /* loop count */
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11:
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sll v0, t2, 5
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mtcr zero, t0
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ori v1, v0, 0x3 /* way0 | write_enable | write_active */
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mtcr v1, t1
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12:
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mfcr v1, t1
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andi v1, 0x1 /* wait for write_active == 0 */
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bnez v1, 12b
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nop
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mtcr zero, t0
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ori v1, v0, 0x7 /* way1 | write_enable | write_active */
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mtcr v1, t1
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13:
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mfcr v1, t1
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andi v1, 0x1 /* wait for write_active == 0 */
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bnez v1, 13b
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nop
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addi t2, 1
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bne t3, t2, 11b
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nop
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b 17f
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nop
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/* XLPII CPUs, Invalidate all 64k of L1 D-cache */
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15:
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li t0, 0x80000000
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li t1, 0x80010000
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16: cache Index_Writeback_Inv_D, 0(t0)
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addiu t0, t0, 32
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bne t0, t1, 16b
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nop
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17:
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.endm
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/*
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* nlm_reset_entry will be copied to the reset entry point for
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* XLR and XLP. The XLP cores start here when they are woken up. This
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* is also the NMI entry point.
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*
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* We use scratch reg 6/7 to save k0/k1 and check for NMI first.
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*
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* The data corresponding to reset/NMI is stored at RESET_DATA_PHYS
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* location, this will have the thread mask (used when core is woken up)
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* and the current NMI handler in case we reached here for an NMI.
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*
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* When a core or thread is newly woken up, it marks itself ready and
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* loops in a 'wait'. When the CPU really needs waking up, we send an NMI
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* IPI to it, with the NMI handler set to prom_boot_secondary_cpus
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*/
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.set noreorder
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.set noat
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.set arch=xlr /* for mfcr/mtcr, XLR is sufficient */
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FEXPORT(nlm_reset_entry)
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dmtc0 k0, $22, 6
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dmtc0 k1, $22, 7
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mfc0 k0, CP0_STATUS
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li k1, 0x80000
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and k1, k0, k1
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beqz k1, 1f /* go to real reset entry */
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nop
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li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */
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ld k0, BOOT_NMI_HANDLER(k1)
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jr k0
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nop
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1: /* Entry point on core wakeup */
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mfc0 t0, CP0_EBASE, 0 /* processor ID */
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andi t0, 0xff00
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li t1, 0x1500 /* XLP 9xx */
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beq t0, t1, 2f /* does not need to set coherent */
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nop
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/* set bit in SYS coherent register for the core */
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mfc0 t0, CP0_EBASE, 1
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mfc0 t1, CP0_EBASE, 1
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srl t1, 5
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andi t1, 0x3 /* t1 <- node */
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li t2, 0x40000
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mul t3, t2, t1 /* t3 = node * 0x40000 */
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srl t0, t0, 2
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and t0, t0, 0x7 /* t0 <- core */
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li t1, 0x1
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sll t0, t1, t0
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nor t0, t0, zero /* t0 <- ~(1 << core) */
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li t2, SYS_CPU_COHERENT_BASE
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add t2, t2, t3 /* t2 <- SYS offset for node */
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lw t1, 0(t2)
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and t1, t1, t0
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sw t1, 0(t2)
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/* read back to ensure complete */
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lw t1, 0(t2)
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sync
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2:
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/* Configure LSU on Non-0 Cores. */
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xlp_config_lsu
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/* FALL THROUGH */
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/*
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* Wake up sibling threads from the initial thread in a core.
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*/
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EXPORT(nlm_boot_siblings)
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/* core L1D flush before enable threads */
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xlp_flush_l1_dcache
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/* Enable hw threads by writing to MAP_THREADMODE of the core */
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li t0, CKSEG1ADDR(RESET_DATA_PHYS)
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lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
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li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
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mfcr t2, t0
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or t2, t2, t1
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mtcr t2, t0
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/*
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* The new hardware thread starts at the next instruction
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* For all the cases other than core 0 thread 0, we will
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* jump to the secondary wait function.
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* NOTE: All GPR contents are lost after the mtcr above!
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*/
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mfc0 v0, CP0_EBASE, 1
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andi v0, 0x3ff /* v0 <- node/core */
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beqz v0, 4f /* boot cpu (cpuid == 0)? */
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nop
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/* setup status reg */
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move t1, zero
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#ifdef CONFIG_64BIT
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ori t1, ST0_KX
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#endif
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mtc0 t1, CP0_STATUS
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/* mark CPU ready */
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li t3, CKSEG1ADDR(RESET_DATA_PHYS)
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ADDIU t1, t3, BOOT_CPU_READY
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sll v1, v0, 2
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PTR_ADDU t1, v1
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li t2, 1
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sw t2, 0(t1)
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/* Wait until NMI hits */
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3: wait
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b 3b
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nop
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/*
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* For the boot CPU, we have to restore registers and
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* return
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*/
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4: dmfc0 t0, $4, 2 /* restore SP from UserLocal */
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li t1, 0xfadebeef
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dmtc0 t1, $4, 2 /* restore SP from UserLocal */
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PTR_SUBU sp, t0, PT_SIZE
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RESTORE_ALL
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jr ra
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nop
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EXPORT(nlm_reset_entry_end)
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LEAF(nlm_init_boot_cpu)
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#ifdef CONFIG_CPU_XLP
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xlp_config_lsu
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#endif
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jr ra
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nop
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END(nlm_init_boot_cpu)
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