mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-24 23:19:53 +07:00
13324c42c1
Pull x86 CPU feature updates from Thomas Gleixner: "Updates for x86 CPU features: - Support for UMWAIT/UMONITOR, which allows to use MWAIT and MONITOR instructions in user space to save power e.g. in HPC workloads which spin wait on synchronization points. The maximum time a MWAIT can halt in userspace is controlled by the kernel and can be adjusted by the sysadmin. - Speed up the MTRR handling code on CPUs which support cache self-snooping correctly. On those CPUs the wbinvd() invocations can be omitted which speeds up the MTRR setup by a factor of 50. - Support for the new x86 vendor Zhaoxin who develops processors based on the VIA Centaur technology. - Prevent 'cat /proc/cpuinfo' from affecting isolated NOHZ_FULL CPUs by sending IPIs to retrieve the CPU frequency and use the cached values instead. - The addition and late revert of the FSGSBASE support. The revert was required as it turned out that the code still has hard to diagnose issues. Yet another engineering trainwreck... - Small fixes, cleanups, improvements and the usual new Intel CPU family/model addons" * 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (41 commits) x86/fsgsbase: Revert FSGSBASE support selftests/x86/fsgsbase: Fix some test case bugs x86/entry/64: Fix and clean up paranoid_exit x86/entry/64: Don't compile ignore_sysret if 32-bit emulation is enabled selftests/x86: Test SYSCALL and SYSENTER manually with TF set x86/mtrr: Skip cache flushes on CPUs with cache self-snooping x86/cpu/intel: Clear cache self-snoop capability in CPUs with known errata Documentation/ABI: Document umwait control sysfs interfaces x86/umwait: Add sysfs interface to control umwait maximum time x86/umwait: Add sysfs interface to control umwait C0.2 state x86/umwait: Initialize umwait control values x86/cpufeatures: Enumerate user wait instructions x86/cpu: Disable frequency requests via aperfmperf IPI for nohz_full CPUs x86/acpi/cstate: Add Zhaoxin processors support for cache flush policy in C3 ACPI, x86: Add Zhaoxin processors support for NONSTOP TSC x86/cpu: Create Zhaoxin processors architecture support file x86/cpu: Split Tremont based Atoms from the rest Documentation/x86/64: Add documentation for GS/FS addressing mode x86/elf: Enumerate kernel FSGSBASE capability in AT_HWCAP2 x86/cpu: Enable FSGSBASE on 64bit by default and add a chicken bit ...
131 lines
4.4 KiB
C
131 lines
4.4 KiB
C
/* Declare dependencies between CPUIDs */
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <asm/cpufeature.h>
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struct cpuid_dep {
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unsigned int feature;
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unsigned int depends;
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};
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/*
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* Table of CPUID features that depend on others.
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*
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* This only includes dependencies that can be usefully disabled, not
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* features part of the base set (like FPU).
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*
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* Note this all is not __init / __initdata because it can be
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* called from cpu hotplug. It shouldn't do anything in this case,
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* but it's difficult to tell that to the init reference checker.
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*/
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static const struct cpuid_dep cpuid_deps[] = {
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{ X86_FEATURE_FXSR, X86_FEATURE_FPU },
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{ X86_FEATURE_XSAVEOPT, X86_FEATURE_XSAVE },
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{ X86_FEATURE_XSAVEC, X86_FEATURE_XSAVE },
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{ X86_FEATURE_XSAVES, X86_FEATURE_XSAVE },
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{ X86_FEATURE_AVX, X86_FEATURE_XSAVE },
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{ X86_FEATURE_PKU, X86_FEATURE_XSAVE },
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{ X86_FEATURE_MPX, X86_FEATURE_XSAVE },
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{ X86_FEATURE_XGETBV1, X86_FEATURE_XSAVE },
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{ X86_FEATURE_CMOV, X86_FEATURE_FXSR },
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{ X86_FEATURE_MMX, X86_FEATURE_FXSR },
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{ X86_FEATURE_MMXEXT, X86_FEATURE_MMX },
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{ X86_FEATURE_FXSR_OPT, X86_FEATURE_FXSR },
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{ X86_FEATURE_XSAVE, X86_FEATURE_FXSR },
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{ X86_FEATURE_XMM, X86_FEATURE_FXSR },
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{ X86_FEATURE_XMM2, X86_FEATURE_XMM },
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{ X86_FEATURE_XMM3, X86_FEATURE_XMM2 },
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{ X86_FEATURE_XMM4_1, X86_FEATURE_XMM2 },
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{ X86_FEATURE_XMM4_2, X86_FEATURE_XMM2 },
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{ X86_FEATURE_XMM3, X86_FEATURE_XMM2 },
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{ X86_FEATURE_PCLMULQDQ, X86_FEATURE_XMM2 },
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{ X86_FEATURE_SSSE3, X86_FEATURE_XMM2, },
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{ X86_FEATURE_F16C, X86_FEATURE_XMM2, },
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{ X86_FEATURE_AES, X86_FEATURE_XMM2 },
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{ X86_FEATURE_SHA_NI, X86_FEATURE_XMM2 },
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{ X86_FEATURE_FMA, X86_FEATURE_AVX },
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{ X86_FEATURE_AVX2, X86_FEATURE_AVX, },
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{ X86_FEATURE_AVX512F, X86_FEATURE_AVX, },
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{ X86_FEATURE_AVX512IFMA, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512PF, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512ER, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512CD, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512DQ, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512BW, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512VL, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512VBMI, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512_VBMI2, X86_FEATURE_AVX512VL },
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{ X86_FEATURE_GFNI, X86_FEATURE_AVX512VL },
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{ X86_FEATURE_VAES, X86_FEATURE_AVX512VL },
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{ X86_FEATURE_VPCLMULQDQ, X86_FEATURE_AVX512VL },
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{ X86_FEATURE_AVX512_VNNI, X86_FEATURE_AVX512VL },
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{ X86_FEATURE_AVX512_BITALG, X86_FEATURE_AVX512VL },
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{ X86_FEATURE_AVX512_4VNNIW, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512_4FMAPS, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512_VPOPCNTDQ, X86_FEATURE_AVX512F },
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{ X86_FEATURE_CQM_OCCUP_LLC, X86_FEATURE_CQM_LLC },
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{ X86_FEATURE_CQM_MBM_TOTAL, X86_FEATURE_CQM_LLC },
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{ X86_FEATURE_CQM_MBM_LOCAL, X86_FEATURE_CQM_LLC },
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{ X86_FEATURE_AVX512_BF16, X86_FEATURE_AVX512VL },
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{}
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};
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static inline void clear_feature(struct cpuinfo_x86 *c, unsigned int feature)
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{
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/*
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* Note: This could use the non atomic __*_bit() variants, but the
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* rest of the cpufeature code uses atomics as well, so keep it for
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* consistency. Cleanup all of it separately.
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*/
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if (!c) {
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clear_cpu_cap(&boot_cpu_data, feature);
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set_bit(feature, (unsigned long *)cpu_caps_cleared);
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} else {
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clear_bit(feature, (unsigned long *)c->x86_capability);
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}
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}
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/* Take the capabilities and the BUG bits into account */
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#define MAX_FEATURE_BITS ((NCAPINTS + NBUGINTS) * sizeof(u32) * 8)
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static void do_clear_cpu_cap(struct cpuinfo_x86 *c, unsigned int feature)
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{
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DECLARE_BITMAP(disable, MAX_FEATURE_BITS);
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const struct cpuid_dep *d;
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bool changed;
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if (WARN_ON(feature >= MAX_FEATURE_BITS))
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return;
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clear_feature(c, feature);
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/* Collect all features to disable, handling dependencies */
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memset(disable, 0, sizeof(disable));
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__set_bit(feature, disable);
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/* Loop until we get a stable state. */
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do {
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changed = false;
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for (d = cpuid_deps; d->feature; d++) {
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if (!test_bit(d->depends, disable))
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continue;
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if (__test_and_set_bit(d->feature, disable))
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continue;
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changed = true;
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clear_feature(c, d->feature);
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}
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} while (changed);
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}
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void clear_cpu_cap(struct cpuinfo_x86 *c, unsigned int feature)
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{
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do_clear_cpu_cap(c, feature);
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}
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void setup_clear_cpu_cap(unsigned int feature)
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{
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do_clear_cpu_cap(NULL, feature);
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}
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