linux_dsm_epyc7002/drivers/gpu
Sean Paul 5f79e03b1f drm/msm: dpu: Only check flush register against pending flushes
There exists a case where a flush of a plane/dma may have been triggered
& started from an async commit. If that plane/dma is subsequently disabled
by the next commit, the flush register will continue to hold the flush
bit for the disabled plane. Since the bit remains active,
pending_kickoff_cnt will never decrement and we'll miss frame_done
events.

This patch limits the check of flush_register to include only those bits
which have been updated with the latest commit.

Changes in v2:
- None

Reviewed-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-12-11 13:07:08 -05:00
..
drm drm/msm: dpu: Only check flush register against pending flushes 2018-12-11 13:07:08 -05:00
host1x gpu: host1x: Detach Host1x from IOMMU DMA domain on arm32 2018-09-26 17:11:14 +02:00
ipu-v3 gpu: ipu-v3: image-convert: allow three rows or columns 2018-11-05 14:40:08 +01:00
vga drm-misc-next for v4.21, part 1: 2018-11-19 10:40:33 +10:00
Makefile