mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 00:15:04 +07:00
1bb5fcb1e2
Upcoming change to DT compiler is going to complain about nodes which have a reg property, but have not defined the address in their name. This patch fixes following type of warnings for OMAP2 clock nodes: Warning (unit_address_vs_reg): Node /ocp/cm@48004000/clocks/dpll3_m2_ck has a reg or ranges property, but no unit name Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
1245 lines
26 KiB
Plaintext
1245 lines
26 KiB
Plaintext
/*
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* Device Tree Source for OMAP24xx clock data
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*
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* Copyright (C) 2014 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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&scm_clocks {
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mcbsp1_mux_fck: mcbsp1_mux_fck@4 {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&func_96m_ck>, <&mcbsp_clks>;
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ti,bit-shift = <2>;
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reg = <0x4>;
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};
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mcbsp1_fck: mcbsp1_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
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};
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mcbsp2_mux_fck: mcbsp2_mux_fck@4 {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&func_96m_ck>, <&mcbsp_clks>;
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ti,bit-shift = <6>;
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reg = <0x4>;
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};
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mcbsp2_fck: mcbsp2_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
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};
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};
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&prcm_clocks {
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func_32k_ck: func_32k_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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secure_32k_ck: secure_32k_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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virt_12m_ck: virt_12m_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <12000000>;
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};
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virt_13m_ck: virt_13m_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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};
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virt_19200000_ck: virt_19200000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <19200000>;
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};
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virt_26m_ck: virt_26m_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <26000000>;
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};
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aplls_clkin_ck: aplls_clkin_ck@540 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>;
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ti,bit-shift = <23>;
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reg = <0x0540>;
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};
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aplls_clkin_x2_ck: aplls_clkin_x2_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&aplls_clkin_ck>;
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clock-mult = <2>;
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clock-div = <1>;
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};
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osc_ck: osc_ck@60 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>;
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ti,bit-shift = <6>;
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reg = <0x0060>;
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ti,index-starts-at-one;
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};
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sys_ck: sys_ck@60 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&osc_ck>;
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ti,bit-shift = <6>;
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ti,max-div = <3>;
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reg = <0x0060>;
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ti,index-starts-at-one;
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};
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alt_ck: alt_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <54000000>;
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};
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mcbsp_clks: mcbsp_clks {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0x0>;
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};
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dpll_ck: dpll_ck@500 {
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#clock-cells = <0>;
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compatible = "ti,omap2-dpll-core-clock";
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clocks = <&sys_ck>, <&sys_ck>;
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reg = <0x0500>, <0x0540>;
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};
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apll96_ck: apll96_ck@500 {
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#clock-cells = <0>;
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compatible = "ti,omap2-apll-clock";
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clocks = <&sys_ck>;
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ti,bit-shift = <2>;
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ti,idlest-shift = <8>;
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ti,clock-frequency = <96000000>;
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reg = <0x0500>, <0x0530>, <0x0520>;
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};
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apll54_ck: apll54_ck@500 {
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#clock-cells = <0>;
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compatible = "ti,omap2-apll-clock";
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clocks = <&sys_ck>;
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ti,bit-shift = <6>;
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ti,idlest-shift = <9>;
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ti,clock-frequency = <54000000>;
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reg = <0x0500>, <0x0530>, <0x0520>;
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};
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func_54m_ck: func_54m_ck@540 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&apll54_ck>, <&alt_ck>;
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ti,bit-shift = <5>;
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reg = <0x0540>;
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};
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core_ck: core_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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func_96m_ck: func_96m_ck {
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#clock-cells = <0>;
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};
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apll96_d2_ck: apll96_d2_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&apll96_ck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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func_48m_ck: func_48m_ck@540 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&apll96_d2_ck>, <&alt_ck>;
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ti,bit-shift = <3>;
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reg = <0x0540>;
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};
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func_12m_ck: func_12m_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&func_48m_ck>;
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clock-mult = <1>;
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clock-div = <4>;
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};
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sys_clkout_src_gate: sys_clkout_src_gate@70 {
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#clock-cells = <0>;
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compatible = "ti,composite-no-wait-gate-clock";
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clocks = <&core_ck>;
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ti,bit-shift = <7>;
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reg = <0x0070>;
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};
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sys_clkout_src_mux: sys_clkout_src_mux@70 {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
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reg = <0x0070>;
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};
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sys_clkout_src: sys_clkout_src {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&sys_clkout_src_gate>, <&sys_clkout_src_mux>;
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};
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sys_clkout: sys_clkout@70 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&sys_clkout_src>;
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ti,bit-shift = <3>;
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ti,max-div = <64>;
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reg = <0x0070>;
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ti,index-power-of-two;
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};
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emul_ck: emul_ck@78 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&func_54m_ck>;
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ti,bit-shift = <0>;
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reg = <0x0078>;
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};
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mpu_ck: mpu_ck@140 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&core_ck>;
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ti,max-div = <31>;
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reg = <0x0140>;
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ti,index-starts-at-one;
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};
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dsp_gate_fck: dsp_gate_fck@800 {
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#clock-cells = <0>;
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compatible = "ti,composite-gate-clock";
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clocks = <&core_ck>;
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ti,bit-shift = <0>;
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reg = <0x0800>;
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};
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dsp_div_fck: dsp_div_fck@840 {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&core_ck>;
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reg = <0x0840>;
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};
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dsp_fck: dsp_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&dsp_gate_fck>, <&dsp_div_fck>;
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};
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core_l3_ck: core_l3_ck@240 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&core_ck>;
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ti,max-div = <31>;
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reg = <0x0240>;
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ti,index-starts-at-one;
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};
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gfx_3d_gate_fck: gfx_3d_gate_fck@300 {
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#clock-cells = <0>;
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compatible = "ti,composite-gate-clock";
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clocks = <&core_l3_ck>;
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ti,bit-shift = <2>;
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reg = <0x0300>;
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};
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gfx_3d_div_fck: gfx_3d_div_fck@340 {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&core_l3_ck>;
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ti,max-div = <4>;
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reg = <0x0340>;
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ti,index-starts-at-one;
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};
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gfx_3d_fck: gfx_3d_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&gfx_3d_gate_fck>, <&gfx_3d_div_fck>;
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};
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gfx_2d_gate_fck: gfx_2d_gate_fck@300 {
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#clock-cells = <0>;
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compatible = "ti,composite-gate-clock";
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clocks = <&core_l3_ck>;
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ti,bit-shift = <1>;
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reg = <0x0300>;
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};
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gfx_2d_div_fck: gfx_2d_div_fck@340 {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&core_l3_ck>;
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ti,max-div = <4>;
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reg = <0x0340>;
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ti,index-starts-at-one;
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};
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gfx_2d_fck: gfx_2d_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&gfx_2d_gate_fck>, <&gfx_2d_div_fck>;
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};
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gfx_ick: gfx_ick@310 {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&core_l3_ck>;
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ti,bit-shift = <0>;
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reg = <0x0310>;
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};
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l4_ck: l4_ck@240 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&core_l3_ck>;
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ti,bit-shift = <5>;
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ti,max-div = <3>;
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reg = <0x0240>;
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ti,index-starts-at-one;
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};
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dss_ick: dss_ick@210 {
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#clock-cells = <0>;
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compatible = "ti,omap3-no-wait-interface-clock";
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clocks = <&l4_ck>;
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ti,bit-shift = <0>;
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reg = <0x0210>;
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};
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dss1_gate_fck: dss1_gate_fck@200 {
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#clock-cells = <0>;
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compatible = "ti,composite-no-wait-gate-clock";
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clocks = <&core_ck>;
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ti,bit-shift = <0>;
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reg = <0x0200>;
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};
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core_d2_ck: core_d2_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&core_ck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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core_d3_ck: core_d3_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&core_ck>;
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clock-mult = <1>;
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clock-div = <3>;
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};
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core_d4_ck: core_d4_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&core_ck>;
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clock-mult = <1>;
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clock-div = <4>;
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};
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core_d5_ck: core_d5_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&core_ck>;
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clock-mult = <1>;
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clock-div = <5>;
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};
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core_d6_ck: core_d6_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&core_ck>;
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clock-mult = <1>;
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clock-div = <6>;
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};
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dummy_ck: dummy_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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core_d8_ck: core_d8_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&core_ck>;
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clock-mult = <1>;
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clock-div = <8>;
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};
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core_d9_ck: core_d9_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&core_ck>;
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clock-mult = <1>;
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clock-div = <9>;
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};
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core_d12_ck: core_d12_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&core_ck>;
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clock-mult = <1>;
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clock-div = <12>;
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};
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core_d16_ck: core_d16_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&core_ck>;
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clock-mult = <1>;
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clock-div = <16>;
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};
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dss1_mux_fck: dss1_mux_fck@240 {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&sys_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d5_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>;
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ti,bit-shift = <8>;
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reg = <0x0240>;
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};
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dss1_fck: dss1_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&dss1_gate_fck>, <&dss1_mux_fck>;
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};
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dss2_gate_fck: dss2_gate_fck@200 {
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#clock-cells = <0>;
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compatible = "ti,composite-no-wait-gate-clock";
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clocks = <&func_48m_ck>;
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ti,bit-shift = <1>;
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reg = <0x0200>;
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};
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dss2_mux_fck: dss2_mux_fck@240 {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&sys_ck>, <&func_48m_ck>;
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ti,bit-shift = <13>;
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reg = <0x0240>;
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};
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dss2_fck: dss2_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&dss2_gate_fck>, <&dss2_mux_fck>;
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};
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dss_54m_fck: dss_54m_fck@200 {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&func_54m_ck>;
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ti,bit-shift = <2>;
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reg = <0x0200>;
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};
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ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck@204 {
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#clock-cells = <0>;
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compatible = "ti,composite-gate-clock";
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clocks = <&core_ck>;
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ti,bit-shift = <1>;
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reg = <0x0204>;
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};
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ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck@240 {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&core_ck>;
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ti,bit-shift = <20>;
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reg = <0x0240>;
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};
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ssi_ssr_sst_fck: ssi_ssr_sst_fck {
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#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&ssi_ssr_sst_gate_fck>, <&ssi_ssr_sst_div_fck>;
|
|
};
|
|
|
|
usb_l4_gate_ick: usb_l4_gate_ick@214 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-interface-clock";
|
|
clocks = <&core_l3_ck>;
|
|
ti,bit-shift = <0>;
|
|
reg = <0x0214>;
|
|
};
|
|
|
|
usb_l4_div_ick: usb_l4_div_ick@240 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-divider-clock";
|
|
clocks = <&core_l3_ck>;
|
|
ti,bit-shift = <25>;
|
|
reg = <0x0240>;
|
|
ti,dividers = <0>, <1>, <2>, <0>, <4>;
|
|
};
|
|
|
|
usb_l4_ick: usb_l4_ick {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
|
|
};
|
|
|
|
ssi_l4_ick: ssi_l4_ick@214 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <1>;
|
|
reg = <0x0214>;
|
|
};
|
|
|
|
gpt1_ick: gpt1_ick@410 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&sys_ck>;
|
|
ti,bit-shift = <0>;
|
|
reg = <0x0410>;
|
|
};
|
|
|
|
gpt1_gate_fck: gpt1_gate_fck@400 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-gate-clock";
|
|
clocks = <&func_32k_ck>;
|
|
ti,bit-shift = <0>;
|
|
reg = <0x0400>;
|
|
};
|
|
|
|
gpt1_mux_fck: gpt1_mux_fck@440 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
|
|
reg = <0x0440>;
|
|
};
|
|
|
|
gpt1_fck: gpt1_fck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
|
|
};
|
|
|
|
gpt2_ick: gpt2_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <4>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
gpt2_gate_fck: gpt2_gate_fck@200 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-gate-clock";
|
|
clocks = <&func_32k_ck>;
|
|
ti,bit-shift = <4>;
|
|
reg = <0x0200>;
|
|
};
|
|
|
|
gpt2_mux_fck: gpt2_mux_fck@244 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
|
|
ti,bit-shift = <2>;
|
|
reg = <0x0244>;
|
|
};
|
|
|
|
gpt2_fck: gpt2_fck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
|
|
};
|
|
|
|
gpt3_ick: gpt3_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <5>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
gpt3_gate_fck: gpt3_gate_fck@200 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-gate-clock";
|
|
clocks = <&func_32k_ck>;
|
|
ti,bit-shift = <5>;
|
|
reg = <0x0200>;
|
|
};
|
|
|
|
gpt3_mux_fck: gpt3_mux_fck@244 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
|
|
ti,bit-shift = <4>;
|
|
reg = <0x0244>;
|
|
};
|
|
|
|
gpt3_fck: gpt3_fck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
|
|
};
|
|
|
|
gpt4_ick: gpt4_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <6>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
gpt4_gate_fck: gpt4_gate_fck@200 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-gate-clock";
|
|
clocks = <&func_32k_ck>;
|
|
ti,bit-shift = <6>;
|
|
reg = <0x0200>;
|
|
};
|
|
|
|
gpt4_mux_fck: gpt4_mux_fck@244 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
|
|
ti,bit-shift = <6>;
|
|
reg = <0x0244>;
|
|
};
|
|
|
|
gpt4_fck: gpt4_fck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
|
|
};
|
|
|
|
gpt5_ick: gpt5_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <7>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
gpt5_gate_fck: gpt5_gate_fck@200 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-gate-clock";
|
|
clocks = <&func_32k_ck>;
|
|
ti,bit-shift = <7>;
|
|
reg = <0x0200>;
|
|
};
|
|
|
|
gpt5_mux_fck: gpt5_mux_fck@244 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x0244>;
|
|
};
|
|
|
|
gpt5_fck: gpt5_fck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
|
|
};
|
|
|
|
gpt6_ick: gpt6_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
gpt6_gate_fck: gpt6_gate_fck@200 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-gate-clock";
|
|
clocks = <&func_32k_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x0200>;
|
|
};
|
|
|
|
gpt6_mux_fck: gpt6_mux_fck@244 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
|
|
ti,bit-shift = <10>;
|
|
reg = <0x0244>;
|
|
};
|
|
|
|
gpt6_fck: gpt6_fck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
|
|
};
|
|
|
|
gpt7_ick: gpt7_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <9>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
gpt7_gate_fck: gpt7_gate_fck@200 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-gate-clock";
|
|
clocks = <&func_32k_ck>;
|
|
ti,bit-shift = <9>;
|
|
reg = <0x0200>;
|
|
};
|
|
|
|
gpt7_mux_fck: gpt7_mux_fck@244 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
|
|
ti,bit-shift = <12>;
|
|
reg = <0x0244>;
|
|
};
|
|
|
|
gpt7_fck: gpt7_fck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
|
|
};
|
|
|
|
gpt8_ick: gpt8_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <10>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
gpt8_gate_fck: gpt8_gate_fck@200 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-gate-clock";
|
|
clocks = <&func_32k_ck>;
|
|
ti,bit-shift = <10>;
|
|
reg = <0x0200>;
|
|
};
|
|
|
|
gpt8_mux_fck: gpt8_mux_fck@244 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
|
|
ti,bit-shift = <14>;
|
|
reg = <0x0244>;
|
|
};
|
|
|
|
gpt8_fck: gpt8_fck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
|
|
};
|
|
|
|
gpt9_ick: gpt9_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <11>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
gpt9_gate_fck: gpt9_gate_fck@200 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-gate-clock";
|
|
clocks = <&func_32k_ck>;
|
|
ti,bit-shift = <11>;
|
|
reg = <0x0200>;
|
|
};
|
|
|
|
gpt9_mux_fck: gpt9_mux_fck@244 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
|
|
ti,bit-shift = <16>;
|
|
reg = <0x0244>;
|
|
};
|
|
|
|
gpt9_fck: gpt9_fck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
|
|
};
|
|
|
|
gpt10_ick: gpt10_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <12>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
gpt10_gate_fck: gpt10_gate_fck@200 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-gate-clock";
|
|
clocks = <&func_32k_ck>;
|
|
ti,bit-shift = <12>;
|
|
reg = <0x0200>;
|
|
};
|
|
|
|
gpt10_mux_fck: gpt10_mux_fck@244 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
|
|
ti,bit-shift = <18>;
|
|
reg = <0x0244>;
|
|
};
|
|
|
|
gpt10_fck: gpt10_fck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
|
|
};
|
|
|
|
gpt11_ick: gpt11_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <13>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
gpt11_gate_fck: gpt11_gate_fck@200 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-gate-clock";
|
|
clocks = <&func_32k_ck>;
|
|
ti,bit-shift = <13>;
|
|
reg = <0x0200>;
|
|
};
|
|
|
|
gpt11_mux_fck: gpt11_mux_fck@244 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
|
|
ti,bit-shift = <20>;
|
|
reg = <0x0244>;
|
|
};
|
|
|
|
gpt11_fck: gpt11_fck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
|
|
};
|
|
|
|
gpt12_ick: gpt12_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <14>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
gpt12_gate_fck: gpt12_gate_fck@200 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-gate-clock";
|
|
clocks = <&func_32k_ck>;
|
|
ti,bit-shift = <14>;
|
|
reg = <0x0200>;
|
|
};
|
|
|
|
gpt12_mux_fck: gpt12_mux_fck@244 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
|
|
ti,bit-shift = <22>;
|
|
reg = <0x0244>;
|
|
};
|
|
|
|
gpt12_fck: gpt12_fck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&gpt12_gate_fck>, <&gpt12_mux_fck>;
|
|
};
|
|
|
|
mcbsp1_ick: mcbsp1_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <15>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
mcbsp1_gate_fck: mcbsp1_gate_fck@200 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-gate-clock";
|
|
clocks = <&mcbsp_clks>;
|
|
ti,bit-shift = <15>;
|
|
reg = <0x0200>;
|
|
};
|
|
|
|
mcbsp2_ick: mcbsp2_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <16>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
mcbsp2_gate_fck: mcbsp2_gate_fck@200 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-gate-clock";
|
|
clocks = <&mcbsp_clks>;
|
|
ti,bit-shift = <16>;
|
|
reg = <0x0200>;
|
|
};
|
|
|
|
mcspi1_ick: mcspi1_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <17>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
mcspi1_fck: mcspi1_fck@200 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,wait-gate-clock";
|
|
clocks = <&func_48m_ck>;
|
|
ti,bit-shift = <17>;
|
|
reg = <0x0200>;
|
|
};
|
|
|
|
mcspi2_ick: mcspi2_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <18>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
mcspi2_fck: mcspi2_fck@200 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,wait-gate-clock";
|
|
clocks = <&func_48m_ck>;
|
|
ti,bit-shift = <18>;
|
|
reg = <0x0200>;
|
|
};
|
|
|
|
uart1_ick: uart1_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <21>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
uart1_fck: uart1_fck@200 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,wait-gate-clock";
|
|
clocks = <&func_48m_ck>;
|
|
ti,bit-shift = <21>;
|
|
reg = <0x0200>;
|
|
};
|
|
|
|
uart2_ick: uart2_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <22>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
uart2_fck: uart2_fck@200 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,wait-gate-clock";
|
|
clocks = <&func_48m_ck>;
|
|
ti,bit-shift = <22>;
|
|
reg = <0x0200>;
|
|
};
|
|
|
|
uart3_ick: uart3_ick@214 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <2>;
|
|
reg = <0x0214>;
|
|
};
|
|
|
|
uart3_fck: uart3_fck@204 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,wait-gate-clock";
|
|
clocks = <&func_48m_ck>;
|
|
ti,bit-shift = <2>;
|
|
reg = <0x0204>;
|
|
};
|
|
|
|
gpios_ick: gpios_ick@410 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&sys_ck>;
|
|
ti,bit-shift = <2>;
|
|
reg = <0x0410>;
|
|
};
|
|
|
|
gpios_fck: gpios_fck@400 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,wait-gate-clock";
|
|
clocks = <&func_32k_ck>;
|
|
ti,bit-shift = <2>;
|
|
reg = <0x0400>;
|
|
};
|
|
|
|
mpu_wdt_ick: mpu_wdt_ick@410 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&sys_ck>;
|
|
ti,bit-shift = <3>;
|
|
reg = <0x0410>;
|
|
};
|
|
|
|
mpu_wdt_fck: mpu_wdt_fck@400 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,wait-gate-clock";
|
|
clocks = <&func_32k_ck>;
|
|
ti,bit-shift = <3>;
|
|
reg = <0x0400>;
|
|
};
|
|
|
|
sync_32k_ick: sync_32k_ick@410 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&sys_ck>;
|
|
ti,bit-shift = <1>;
|
|
reg = <0x0410>;
|
|
};
|
|
|
|
wdt1_ick: wdt1_ick@410 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&sys_ck>;
|
|
ti,bit-shift = <4>;
|
|
reg = <0x0410>;
|
|
};
|
|
|
|
omapctrl_ick: omapctrl_ick@410 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&sys_ck>;
|
|
ti,bit-shift = <5>;
|
|
reg = <0x0410>;
|
|
};
|
|
|
|
cam_fck: cam_fck@200 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&func_96m_ck>;
|
|
ti,bit-shift = <31>;
|
|
reg = <0x0200>;
|
|
};
|
|
|
|
cam_ick: cam_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-no-wait-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <31>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
mailboxes_ick: mailboxes_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <30>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
wdt4_ick: wdt4_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <29>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
wdt4_fck: wdt4_fck@200 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,wait-gate-clock";
|
|
clocks = <&func_32k_ck>;
|
|
ti,bit-shift = <29>;
|
|
reg = <0x0200>;
|
|
};
|
|
|
|
mspro_ick: mspro_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <27>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
mspro_fck: mspro_fck@200 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,wait-gate-clock";
|
|
clocks = <&func_96m_ck>;
|
|
ti,bit-shift = <27>;
|
|
reg = <0x0200>;
|
|
};
|
|
|
|
fac_ick: fac_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <25>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
fac_fck: fac_fck@200 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,wait-gate-clock";
|
|
clocks = <&func_12m_ck>;
|
|
ti,bit-shift = <25>;
|
|
reg = <0x0200>;
|
|
};
|
|
|
|
hdq_ick: hdq_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <23>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
hdq_fck: hdq_fck@200 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,wait-gate-clock";
|
|
clocks = <&func_12m_ck>;
|
|
ti,bit-shift = <23>;
|
|
reg = <0x0200>;
|
|
};
|
|
|
|
i2c1_ick: i2c1_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <19>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
i2c2_ick: i2c2_ick@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <20>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
gpmc_fck: gpmc_fck@238 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,fixed-factor-clock";
|
|
clocks = <&core_l3_ck>;
|
|
ti,clock-div = <1>;
|
|
ti,autoidle-shift = <1>;
|
|
reg = <0x0238>;
|
|
ti,clock-mult = <1>;
|
|
};
|
|
|
|
sdma_fck: sdma_fck {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&core_l3_ck>;
|
|
clock-mult = <1>;
|
|
clock-div = <1>;
|
|
};
|
|
|
|
sdma_ick: sdma_ick@238 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,fixed-factor-clock";
|
|
clocks = <&core_l3_ck>;
|
|
ti,clock-div = <1>;
|
|
ti,autoidle-shift = <0>;
|
|
reg = <0x0238>;
|
|
ti,clock-mult = <1>;
|
|
};
|
|
|
|
sdrc_ick: sdrc_ick@238 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,fixed-factor-clock";
|
|
clocks = <&core_l3_ck>;
|
|
ti,clock-div = <1>;
|
|
ti,autoidle-shift = <2>;
|
|
reg = <0x0238>;
|
|
ti,clock-mult = <1>;
|
|
};
|
|
|
|
des_ick: des_ick@21c {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <0>;
|
|
reg = <0x021c>;
|
|
};
|
|
|
|
sha_ick: sha_ick@21c {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <1>;
|
|
reg = <0x021c>;
|
|
};
|
|
|
|
rng_ick: rng_ick@21c {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <2>;
|
|
reg = <0x021c>;
|
|
};
|
|
|
|
aes_ick: aes_ick@21c {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <3>;
|
|
reg = <0x021c>;
|
|
};
|
|
|
|
pka_ick: pka_ick@21c {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <4>;
|
|
reg = <0x021c>;
|
|
};
|
|
|
|
usb_fck: usb_fck@204 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,wait-gate-clock";
|
|
clocks = <&func_48m_ck>;
|
|
ti,bit-shift = <0>;
|
|
reg = <0x0204>;
|
|
};
|
|
};
|