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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e3b8bbb9e8
In PG2.0 there is an issue where PHY's FDSP Code RAM sometimes gets corrupted when exiting from ELP mode. This issue is related to FDSP Code RAM clock implementation. PG2.1 introduces a HW fix for this issue that requires the driver to change the FDSP Code Ram clock settings (mux it to ATGP clock instead of its own clock). This workaround uses PHY_FPGA_SPARE_1 register and is relevant to WL8 PG2.1 devices. The fix is also backward compatible with older PG2.0 devices where the register PHY_FPGA_SPARE_1 is not used and not connected. The fix is done in the wl18xx_pre_upload function (must be performed before uploading the FW code) and includes the following steps: 1. Disable FDSP clock 2. Set ATPG clock toward FDSP Code RAM rather than its own clock. 3. Re-enable FDSP clock Signed-off-by: Yair Shapira <yair.shapira@ti.com> Signed-off-by: Ido Reis <idor@ti.com> Signed-off-by: Arik Nemtsov <arik@wizery.com> Signed-off-by: Luciano Coelho <coelho@ti.com>
236 lines
8.1 KiB
C
236 lines
8.1 KiB
C
/*
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* This file is part of wlcore
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*
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* Copyright (C) 2011 Texas Instruments Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef __REG_H__
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#define __REG_H__
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#define WL18XX_REGISTERS_BASE 0x00800000
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#define WL18XX_CODE_BASE 0x00000000
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#define WL18XX_DATA_BASE 0x00400000
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#define WL18XX_DOUBLE_BUFFER_BASE 0x00600000
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#define WL18XX_MCU_KEY_SEARCH_BASE 0x00700000
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#define WL18XX_PHY_BASE 0x00900000
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#define WL18XX_TOP_OCP_BASE 0x00A00000
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#define WL18XX_PACKET_RAM_BASE 0x00B00000
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#define WL18XX_HOST_BASE 0x00C00000
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#define WL18XX_REGISTERS_DOWN_SIZE 0x0000B000
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#define WL18XX_REG_BOOT_PART_START 0x00802000
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#define WL18XX_REG_BOOT_PART_SIZE 0x00014578
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#define WL18XX_PHY_INIT_MEM_ADDR 0x80926000
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#define WL18XX_PHY_END_MEM_ADDR 0x8093CA44
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#define WL18XX_PHY_INIT_MEM_SIZE \
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(WL18XX_PHY_END_MEM_ADDR - WL18XX_PHY_INIT_MEM_ADDR)
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#define WL18XX_SDIO_WSPI_BASE (WL18XX_REGISTERS_BASE)
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#define WL18XX_REG_CONFIG_BASE (WL18XX_REGISTERS_BASE + 0x02000)
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#define WL18XX_WGCM_REGS_BASE (WL18XX_REGISTERS_BASE + 0x03000)
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#define WL18XX_ENC_BASE (WL18XX_REGISTERS_BASE + 0x04000)
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#define WL18XX_INTERRUPT_BASE (WL18XX_REGISTERS_BASE + 0x05000)
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#define WL18XX_UART_BASE (WL18XX_REGISTERS_BASE + 0x06000)
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#define WL18XX_WELP_BASE (WL18XX_REGISTERS_BASE + 0x07000)
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#define WL18XX_TCP_CKSM_BASE (WL18XX_REGISTERS_BASE + 0x08000)
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#define WL18XX_FIFO_BASE (WL18XX_REGISTERS_BASE + 0x09000)
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#define WL18XX_OCP_BRIDGE_BASE (WL18XX_REGISTERS_BASE + 0x0A000)
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#define WL18XX_PMAC_RX_BASE (WL18XX_REGISTERS_BASE + 0x14800)
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#define WL18XX_PMAC_ACM_BASE (WL18XX_REGISTERS_BASE + 0x14C00)
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#define WL18XX_PMAC_TX_BASE (WL18XX_REGISTERS_BASE + 0x15000)
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#define WL18XX_PMAC_CSR_BASE (WL18XX_REGISTERS_BASE + 0x15400)
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#define WL18XX_REG_ECPU_CONTROL (WL18XX_REGISTERS_BASE + 0x02004)
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#define WL18XX_REG_INTERRUPT_NO_CLEAR (WL18XX_REGISTERS_BASE + 0x050E8)
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#define WL18XX_REG_INTERRUPT_ACK (WL18XX_REGISTERS_BASE + 0x050F0)
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#define WL18XX_REG_INTERRUPT_TRIG (WL18XX_REGISTERS_BASE + 0x5074)
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#define WL18XX_REG_INTERRUPT_TRIG_H (WL18XX_REGISTERS_BASE + 0x5078)
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#define WL18XX_REG_INTERRUPT_MASK (WL18XX_REGISTERS_BASE + 0x0050DC)
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#define WL18XX_REG_CHIP_ID_B (WL18XX_REGISTERS_BASE + 0x01542C)
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#define WL18XX_SLV_MEM_DATA (WL18XX_HOST_BASE + 0x0018)
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#define WL18XX_SLV_REG_DATA (WL18XX_HOST_BASE + 0x0008)
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/* Scratch Pad registers*/
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#define WL18XX_SCR_PAD0 (WL18XX_REGISTERS_BASE + 0x0154EC)
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#define WL18XX_SCR_PAD1 (WL18XX_REGISTERS_BASE + 0x0154F0)
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#define WL18XX_SCR_PAD2 (WL18XX_REGISTERS_BASE + 0x0154F4)
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#define WL18XX_SCR_PAD3 (WL18XX_REGISTERS_BASE + 0x0154F8)
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#define WL18XX_SCR_PAD4 (WL18XX_REGISTERS_BASE + 0x0154FC)
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#define WL18XX_SCR_PAD4_SET (WL18XX_REGISTERS_BASE + 0x015504)
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#define WL18XX_SCR_PAD4_CLR (WL18XX_REGISTERS_BASE + 0x015500)
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#define WL18XX_SCR_PAD5 (WL18XX_REGISTERS_BASE + 0x015508)
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#define WL18XX_SCR_PAD5_SET (WL18XX_REGISTERS_BASE + 0x015510)
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#define WL18XX_SCR_PAD5_CLR (WL18XX_REGISTERS_BASE + 0x01550C)
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#define WL18XX_SCR_PAD6 (WL18XX_REGISTERS_BASE + 0x015514)
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#define WL18XX_SCR_PAD7 (WL18XX_REGISTERS_BASE + 0x015518)
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#define WL18XX_SCR_PAD8 (WL18XX_REGISTERS_BASE + 0x01551C)
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#define WL18XX_SCR_PAD9 (WL18XX_REGISTERS_BASE + 0x015520)
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/* Spare registers*/
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#define WL18XX_SPARE_A1 (WL18XX_REGISTERS_BASE + 0x002194)
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#define WL18XX_SPARE_A2 (WL18XX_REGISTERS_BASE + 0x002198)
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#define WL18XX_SPARE_A3 (WL18XX_REGISTERS_BASE + 0x00219C)
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#define WL18XX_SPARE_A4 (WL18XX_REGISTERS_BASE + 0x0021A0)
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#define WL18XX_SPARE_A5 (WL18XX_REGISTERS_BASE + 0x0021A4)
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#define WL18XX_SPARE_A6 (WL18XX_REGISTERS_BASE + 0x0021A8)
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#define WL18XX_SPARE_A7 (WL18XX_REGISTERS_BASE + 0x0021AC)
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#define WL18XX_SPARE_A8 (WL18XX_REGISTERS_BASE + 0x0021B0)
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#define WL18XX_SPARE_B1 (WL18XX_REGISTERS_BASE + 0x015524)
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#define WL18XX_SPARE_B2 (WL18XX_REGISTERS_BASE + 0x015528)
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#define WL18XX_SPARE_B3 (WL18XX_REGISTERS_BASE + 0x01552C)
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#define WL18XX_SPARE_B4 (WL18XX_REGISTERS_BASE + 0x015530)
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#define WL18XX_SPARE_B5 (WL18XX_REGISTERS_BASE + 0x015534)
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#define WL18XX_SPARE_B6 (WL18XX_REGISTERS_BASE + 0x015538)
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#define WL18XX_SPARE_B7 (WL18XX_REGISTERS_BASE + 0x01553C)
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#define WL18XX_SPARE_B8 (WL18XX_REGISTERS_BASE + 0x015540)
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#define WL18XX_REG_COMMAND_MAILBOX_PTR (WL18XX_SCR_PAD0)
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#define WL18XX_REG_EVENT_MAILBOX_PTR (WL18XX_SCR_PAD1)
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#define WL18XX_EEPROMLESS_IND (WL18XX_SCR_PAD4)
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#define WL18XX_WELP_ARM_COMMAND (WL18XX_REGISTERS_BASE + 0x7100)
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#define WL18XX_ENABLE (WL18XX_REGISTERS_BASE + 0x01543C)
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/* PRCM registers */
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#define PLATFORM_DETECTION 0xA0E3E0
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#define OCS_EN 0xA02080
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#define PRIMARY_CLK_DETECT 0xA020A6
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#define PLLSH_WCS_PLL_N 0xA02362
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#define PLLSH_WCS_PLL_M 0xA02360
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#define PLLSH_WCS_PLL_Q_FACTOR_CFG_1 0xA02364
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#define PLLSH_WCS_PLL_Q_FACTOR_CFG_2 0xA02366
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#define PLLSH_WCS_PLL_P_FACTOR_CFG_1 0xA02368
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#define PLLSH_WCS_PLL_P_FACTOR_CFG_2 0xA0236A
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#define PLLSH_WCS_PLL_SWALLOW_EN 0xA0236C
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#define PLLSH_WL_PLL_EN 0xA02392
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#define PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK 0xFFFF
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#define PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK 0x007F
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#define PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK 0xFFFF
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#define PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK 0x000F
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#define PLLSH_WCS_PLL_SWALLOW_EN_VAL1 0x1
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#define PLLSH_WCS_PLL_SWALLOW_EN_VAL2 0x12
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#define WL18XX_REG_FUSE_DATA_1_3 0xA0260C
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#define WL18XX_PG_VER_MASK 0x70
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#define WL18XX_PG_VER_OFFSET 4
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#define WL18XX_ROM_VER_MASK 0x3
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#define WL18XX_ROM_VER_OFFSET 0
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#define WL18XX_METAL_VER_MASK 0xC
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#define WL18XX_METAL_VER_OFFSET 2
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#define WL18XX_NEW_METAL_VER_MASK 0x180
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#define WL18XX_NEW_METAL_VER_OFFSET 7
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#define WL18XX_REG_FUSE_DATA_2_3 0xA02614
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#define WL18XX_RDL_VER_MASK 0x1f00
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#define WL18XX_RDL_VER_OFFSET 8
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#define WL18XX_REG_FUSE_BD_ADDR_1 0xA02602
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#define WL18XX_REG_FUSE_BD_ADDR_2 0xA02606
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#define WL18XX_CMD_MBOX_ADDRESS 0xB007B4
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#define WL18XX_FW_STATUS_ADDR 0x50F8
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#define CHIP_ID_185x_PG10 (0x06030101)
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#define CHIP_ID_185x_PG20 (0x06030111)
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/*
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* Host Command Interrupt. Setting this bit masks
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* the interrupt that the host issues to inform
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* the FW that it has sent a command
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* to the Wlan hardware Command Mailbox.
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*/
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#define WL18XX_INTR_TRIG_CMD BIT(28)
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/*
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* Host Event Acknowlegde Interrupt. The host
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* sets this bit to acknowledge that it received
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* the unsolicited information from the event
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* mailbox.
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*/
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#define WL18XX_INTR_TRIG_EVENT_ACK BIT(29)
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/*
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* To boot the firmware in PLT mode we need to write this value in
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* SCR_PAD8 before starting.
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*/
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#define WL18XX_SCR_PAD8_PLT 0xBABABEBE
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enum {
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COMPONENT_NO_SWITCH = 0x0,
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COMPONENT_2_WAY_SWITCH = 0x1,
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COMPONENT_3_WAY_SWITCH = 0x2,
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COMPONENT_MATCHING = 0x3,
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};
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enum {
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FEM_NONE = 0x0,
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FEM_VENDOR_1 = 0x1,
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FEM_VENDOR_2 = 0x2,
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FEM_VENDOR_3 = 0x3,
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};
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enum {
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BOARD_TYPE_EVB_18XX = 0,
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BOARD_TYPE_DVP_18XX = 1,
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BOARD_TYPE_HDK_18XX = 2,
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BOARD_TYPE_FPGA_18XX = 3,
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BOARD_TYPE_COM8_18XX = 4,
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NUM_BOARD_TYPES,
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};
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enum {
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RDL_NONE = 0,
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RDL_1_HP = 1,
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RDL_2_SP = 2,
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RDL_3_HP = 3,
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RDL_4_SP = 4,
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_RDL_LAST,
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RDL_MAX = _RDL_LAST - 1,
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};
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static const char * const rdl_names[] = {
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[RDL_NONE] = "",
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[RDL_1_HP] = "1853 SISO",
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[RDL_2_SP] = "1857 MIMO",
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[RDL_3_HP] = "1893 SISO",
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[RDL_4_SP] = "1897 MIMO",
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};
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/* FPGA_SPARE_1 register - used to change the PHY ATPG clock at boot time */
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#define WL18XX_PHY_FPGA_SPARE_1 0x8093CA40
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/* command to disable FDSP clock */
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#define MEM_FDSP_CLK_120_DISABLE 0x80000000
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/* command to set ATPG clock toward FDSP Code RAM rather than its own clock */
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#define MEM_FDSP_CODERAM_FUNC_CLK_SEL 0xC0000000
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/* command to re-enable FDSP clock */
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#define MEM_FDSP_CLK_120_ENABLE 0x40000000
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#endif /* __REG_H__ */
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