mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 00:40:55 +07:00
2ed0ef543a
* Return 0 instead of dev->irq in ->init_chipset implementations. * Fix ->init_chipset method to return 'int' value instead of 'unsigned int' one. This fixes ->init_chipset handling for host drivers (cs5530, hpt366 and pdc202xx_new) for which it is possible for this method to fail. Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
474 lines
14 KiB
C
474 lines
14 KiB
C
/*
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* Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
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* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 2003 Red Hat
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* Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
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*
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* May be copied or modified under the terms of the GNU General Public License
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*
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* Documentation:
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*
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* Publically available from Intel web site. Errata documentation
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* is also publically available. As an aide to anyone hacking on this
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* driver the list of errata that are relevant is below.going back to
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* PIIX4. Older device documentation is now a bit tricky to find.
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*
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* Errata of note:
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*
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* Unfixable
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* PIIX4 errata #9 - Only on ultra obscure hw
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* ICH3 errata #13 - Not observed to affect real hw
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* by Intel
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*
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* Things we must deal with
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* PIIX4 errata #10 - BM IDE hang with non UDMA
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* (must stop/start dma to recover)
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* 440MX errata #15 - As PIIX4 errata #10
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* PIIX4 errata #15 - Must not read control registers
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* during a PIO transfer
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* 440MX errata #13 - As PIIX4 errata #15
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* ICH2 errata #21 - DMA mode 0 doesn't work right
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* ICH0/1 errata #55 - As ICH2 errata #21
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* ICH2 spec c #9 - Extra operations needed to handle
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* drive hotswap [NOT YET SUPPORTED]
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* ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
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* and must be dword aligned
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* ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
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*
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* Should have been BIOS fixed:
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* 450NX: errata #19 - DMA hangs on old 450NX
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* 450NX: errata #20 - DMA hangs on old 450NX
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* 450NX: errata #25 - Corruption with DMA on old 450NX
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* ICH3 errata #15 - IDE deadlock under high load
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* (BIOS must set dev 31 fn 0 bit 23)
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* ICH3 errata #18 - Don't use native mode
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/ide.h>
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#include <linux/init.h>
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#include <asm/io.h>
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#define DRV_NAME "piix"
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static int no_piix_dma;
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/**
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* piix_set_pio_mode - set host controller for PIO mode
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* @drive: drive
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* @pio: PIO mode number
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*
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* Set the interface PIO mode based upon the settings done by AMI BIOS.
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*/
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static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio)
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{
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ide_hwif_t *hwif = drive->hwif;
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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int is_slave = drive->dn & 1;
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int master_port = hwif->channel ? 0x42 : 0x40;
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int slave_port = 0x44;
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unsigned long flags;
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u16 master_data;
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u8 slave_data;
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static DEFINE_SPINLOCK(tune_lock);
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int control = 0;
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/* ISP RTC */
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static const u8 timings[][2]= {
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{ 0, 0 },
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{ 0, 0 },
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{ 1, 0 },
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{ 2, 1 },
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{ 2, 3 }, };
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/*
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* Master vs slave is synchronized above us but the slave register is
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* shared by the two hwifs so the corner case of two slave timeouts in
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* parallel must be locked.
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*/
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spin_lock_irqsave(&tune_lock, flags);
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pci_read_config_word(dev, master_port, &master_data);
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if (pio > 1)
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control |= 1; /* Programmable timing on */
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if (drive->media == ide_disk)
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control |= 4; /* Prefetch, post write */
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if (pio > 2)
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control |= 2; /* IORDY */
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if (is_slave) {
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master_data |= 0x4000;
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master_data &= ~0x0070;
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if (pio > 1) {
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/* Set PPE, IE and TIME */
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master_data |= control << 4;
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}
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pci_read_config_byte(dev, slave_port, &slave_data);
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slave_data &= hwif->channel ? 0x0f : 0xf0;
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slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
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(hwif->channel ? 4 : 0);
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} else {
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master_data &= ~0x3307;
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if (pio > 1) {
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/* enable PPE, IE and TIME */
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master_data |= control;
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}
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master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
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}
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pci_write_config_word(dev, master_port, master_data);
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if (is_slave)
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pci_write_config_byte(dev, slave_port, slave_data);
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spin_unlock_irqrestore(&tune_lock, flags);
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}
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/**
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* piix_set_dma_mode - set host controller for DMA mode
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* @drive: drive
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* @speed: DMA mode
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*
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* Set a PIIX host controller to the desired DMA mode. This involves
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* programming the right timing data into the PCI configuration space.
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*/
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static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
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{
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ide_hwif_t *hwif = drive->hwif;
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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u8 maslave = hwif->channel ? 0x42 : 0x40;
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int a_speed = 3 << (drive->dn * 4);
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int u_flag = 1 << drive->dn;
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int v_flag = 0x01 << drive->dn;
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int w_flag = 0x10 << drive->dn;
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int u_speed = 0;
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int sitre;
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u16 reg4042, reg4a;
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u8 reg48, reg54, reg55;
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pci_read_config_word(dev, maslave, ®4042);
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sitre = (reg4042 & 0x4000) ? 1 : 0;
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pci_read_config_byte(dev, 0x48, ®48);
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pci_read_config_word(dev, 0x4a, ®4a);
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pci_read_config_byte(dev, 0x54, ®54);
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pci_read_config_byte(dev, 0x55, ®55);
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if (speed >= XFER_UDMA_0) {
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u8 udma = speed - XFER_UDMA_0;
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u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);
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if (!(reg48 & u_flag))
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pci_write_config_byte(dev, 0x48, reg48 | u_flag);
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if (speed == XFER_UDMA_5) {
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pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
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} else {
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pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
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}
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if ((reg4a & a_speed) != u_speed)
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pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
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if (speed > XFER_UDMA_2) {
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if (!(reg54 & v_flag))
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pci_write_config_byte(dev, 0x54, reg54 | v_flag);
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} else
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pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
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} else {
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const u8 mwdma_to_pio[] = { 0, 3, 4 };
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u8 pio;
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if (reg48 & u_flag)
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pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
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if (reg4a & a_speed)
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pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
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if (reg54 & v_flag)
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pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
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if (reg55 & w_flag)
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pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
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if (speed >= XFER_MW_DMA_0)
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pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
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else
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pio = 2; /* only SWDMA2 is allowed */
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piix_set_pio_mode(drive, pio);
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}
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}
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/**
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* init_chipset_ich - set up the ICH chipset
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* @dev: PCI device to set up
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*
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* Initialize the PCI device as required. For the ICH this turns
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* out to be nice and simple.
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*/
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static int init_chipset_ich(struct pci_dev *dev)
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{
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u32 extra = 0;
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pci_read_config_dword(dev, 0x54, &extra);
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pci_write_config_dword(dev, 0x54, extra | 0x400);
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return 0;
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}
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/**
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* ich_clear_irq - clear BMDMA status
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* @drive: IDE drive
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*
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* ICHx contollers set DMA INTR no matter DMA or PIO.
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* BMDMA status might need to be cleared even for
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* PIO interrupts to prevent spurious/lost IRQ.
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*/
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static void ich_clear_irq(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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u8 dma_stat;
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/*
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* ide_dma_end() needs BMDMA status for error checking.
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* So, skip clearing BMDMA status here and leave it
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* to ide_dma_end() if this is DMA interrupt.
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*/
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if (drive->waiting_for_dma || hwif->dma_base == 0)
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return;
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/* clear the INTR & ERROR bits */
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dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
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/* Should we force the bit as well ? */
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outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS);
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}
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struct ich_laptop {
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u16 device;
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u16 subvendor;
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u16 subdevice;
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};
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/*
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* List of laptops that use short cables rather than 80 wire
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*/
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static const struct ich_laptop ich_laptop[] = {
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/* devid, subvendor, subdev */
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{ 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
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{ 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
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{ 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
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{ 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
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{ 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
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{ 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
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{ 0x24CA, 0x1025, 0x0061 }, /* ICH4 on Acer Aspire 2023WLMi */
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{ 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
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{ 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
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{ 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
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/* end marker */
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{ 0, }
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};
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static u8 piix_cable_detect(ide_hwif_t *hwif)
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{
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struct pci_dev *pdev = to_pci_dev(hwif->dev);
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const struct ich_laptop *lap = &ich_laptop[0];
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u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;
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/* check for specials */
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while (lap->device) {
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if (lap->device == pdev->device &&
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lap->subvendor == pdev->subsystem_vendor &&
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lap->subdevice == pdev->subsystem_device) {
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return ATA_CBL_PATA40_SHORT;
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}
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lap++;
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}
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pci_read_config_byte(pdev, 0x54, ®54h);
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return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
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}
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/**
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* init_hwif_piix - fill in the hwif for the PIIX
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* @hwif: IDE interface
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*
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* Set up the ide_hwif_t for the PIIX interface according to the
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* capabilities of the hardware.
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*/
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static void __devinit init_hwif_piix(ide_hwif_t *hwif)
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{
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if (!hwif->dma_base)
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return;
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if (no_piix_dma)
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hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
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}
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static const struct ide_port_ops piix_port_ops = {
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.set_pio_mode = piix_set_pio_mode,
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.set_dma_mode = piix_set_dma_mode,
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.cable_detect = piix_cable_detect,
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};
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static const struct ide_port_ops ich_port_ops = {
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.set_pio_mode = piix_set_pio_mode,
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.set_dma_mode = piix_set_dma_mode,
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.clear_irq = ich_clear_irq,
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.cable_detect = piix_cable_detect,
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};
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#define DECLARE_PIIX_DEV(udma) \
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{ \
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.name = DRV_NAME, \
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.init_hwif = init_hwif_piix, \
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.enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
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.port_ops = &piix_port_ops, \
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.pio_mask = ATA_PIO4, \
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.swdma_mask = ATA_SWDMA2_ONLY, \
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.mwdma_mask = ATA_MWDMA12_ONLY, \
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.udma_mask = udma, \
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}
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#define DECLARE_ICH_DEV(udma) \
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{ \
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.name = DRV_NAME, \
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.init_chipset = init_chipset_ich, \
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.init_hwif = init_hwif_piix, \
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.enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
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.port_ops = &ich_port_ops, \
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.pio_mask = ATA_PIO4, \
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.swdma_mask = ATA_SWDMA2_ONLY, \
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.mwdma_mask = ATA_MWDMA12_ONLY, \
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.udma_mask = udma, \
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}
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static const struct ide_port_info piix_pci_info[] __devinitdata = {
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/* 0: MPIIX */
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{ /*
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* MPIIX actually has only a single IDE channel mapped to
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* the primary or secondary ports depending on the value
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* of the bit 14 of the IDETIM register at offset 0x6c
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*/
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.name = DRV_NAME,
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.enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
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.host_flags = IDE_HFLAG_ISA_PORTS | IDE_HFLAG_NO_DMA,
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.pio_mask = ATA_PIO4,
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/* This is a painful system best to let it self tune for now */
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},
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/* 1: PIIXa/PIIXb/PIIX3 */
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DECLARE_PIIX_DEV(0x00), /* no udma */
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/* 2: PIIX4 */
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DECLARE_PIIX_DEV(ATA_UDMA2),
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/* 3: ICH0 */
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DECLARE_ICH_DEV(ATA_UDMA2),
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/* 4: ICH */
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DECLARE_ICH_DEV(ATA_UDMA4),
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/* 5: PIIX4 */
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DECLARE_PIIX_DEV(ATA_UDMA4),
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/* 6: ICH[2-7]/ICH[2-3]M/C-ICH/ICH5-SATA/ESB2/ICH8M */
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DECLARE_ICH_DEV(ATA_UDMA5),
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};
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/**
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* piix_init_one - called when a PIIX is found
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* @dev: the piix device
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* @id: the matching pci id
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*
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* Called when the PCI registration layer (or the IDE initialization)
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* finds a device matching our IDE device tables.
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*/
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static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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return ide_pci_init_one(dev, &piix_pci_info[id->driver_data], NULL);
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}
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/**
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* piix_check_450nx - Check for problem 450NX setup
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*
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* Check for the present of 450NX errata #19 and errata #25. If
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* they are found, disable use of DMA IDE
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*/
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static void __devinit piix_check_450nx(void)
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{
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struct pci_dev *pdev = NULL;
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u16 cfg;
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while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
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{
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/* Look for 450NX PXB. Check for problem configurations
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A PCI quirk checks bit 6 already */
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pci_read_config_word(pdev, 0x41, &cfg);
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/* Only on the original revision: IDE DMA can hang */
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if (pdev->revision == 0x00)
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no_piix_dma = 1;
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/* On all revisions below 5 PXB bus lock must be disabled for IDE */
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else if (cfg & (1<<14) && pdev->revision < 5)
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no_piix_dma = 2;
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}
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if(no_piix_dma)
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printk(KERN_WARNING DRV_NAME ": 450NX errata present, disabling IDE DMA.\n");
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if(no_piix_dma == 2)
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printk(KERN_WARNING DRV_NAME ": A BIOS update may resolve this.\n");
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}
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static const struct pci_device_id piix_pci_tbl[] = {
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_0), 1 },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_1), 1 },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), 0 },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371SB_1), 1 },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371AB), 2 },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AB_1), 3 },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82443MX_1), 2 },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AA_1), 4 },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82372FB_1), 5 },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82451NX), 2 },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_9), 6 },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_8), 6 },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_10), 6 },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_11), 6 },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_11), 6 },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_11), 6 },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801E_11), 6 },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_10), 6 },
|
|
#ifdef CONFIG_BLK_DEV_IDE_SATA
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|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_1), 6 },
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|
#endif
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB_2), 6 },
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH6_19), 6 },
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH7_21), 6 },
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_1), 6 },
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB2_18), 6 },
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH8_6), 6 },
|
|
{ 0, },
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
|
|
|
|
static struct pci_driver piix_pci_driver = {
|
|
.name = "PIIX_IDE",
|
|
.id_table = piix_pci_tbl,
|
|
.probe = piix_init_one,
|
|
.remove = ide_pci_remove,
|
|
.suspend = ide_pci_suspend,
|
|
.resume = ide_pci_resume,
|
|
};
|
|
|
|
static int __init piix_ide_init(void)
|
|
{
|
|
piix_check_450nx();
|
|
return ide_pci_register_driver(&piix_pci_driver);
|
|
}
|
|
|
|
static void __exit piix_ide_exit(void)
|
|
{
|
|
pci_unregister_driver(&piix_pci_driver);
|
|
}
|
|
|
|
module_init(piix_ide_init);
|
|
module_exit(piix_ide_exit);
|
|
|
|
MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
|
|
MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
|
|
MODULE_LICENSE("GPL");
|