Luke Nelson 5f316b65e9 riscv, bpf: Add RV32G eBPF JIT ... This is an eBPF JIT for RV32G, adapted from the JIT for RV64G and the 32-bit ARM JIT. There are two main changes required for this to work compared to the RV64 JIT. First, eBPF registers are 64-bit, while RV32G registers are 32-bit. BPF registers either map directly to 2 RISC-V registers, or reside in stack scratch space and are saved and restored when used. Second, many 64-bit ALU operations do not trivially map to 32-bit operations. Operations that move bits between high and low words, such as ADD, LSH, MUL, and others must emulate the 64-bit behavior in terms of 32-bit instructions. This patch also makes related changes to bpf_jit.h, such as adding RISC-V instructions required by the RV32 JIT. Supported features: The RV32 JIT supports the same features and instructions as the RV64 JIT, with the following exceptions: - ALU64 DIV/MOD: Requires loops to implement on 32-bit hardware. - BPF_XADD | BPF_DW: There's no 8-byte atomic instruction in RV32. These features are also unsupported on other BPF JITs for 32-bit architectures. Testing: - lib/test_bpf.c test_bpf: Summary: 378 PASSED, 0 FAILED, [349/366 JIT'ed] test_bpf: test_skb_segment: Summary: 2 PASSED, 0 FAILED The tests that are not JITed are all due to use of 64-bit div/mod or 64-bit xadd. - tools/testing/selftests/bpf/test_verifier.c Summary: 1415 PASSED, 122 SKIPPED, 43 FAILED Tested both with and without BPF JIT hardening. This is the same set of tests that pass using the BPF interpreter with the JIT disabled. Verification and synthesis: We developed the RV32 JIT using our automated verification tool, Serval. We have used Serval in the past to verify patches to the RV64 JIT. We also used Serval to superoptimize the resulting code through program synthesis. You can find the tool and a guide to the approach and results here: https://github.com/uw-unsat/serval-bpf/tree/rv32-jit-v5 Co-developed-by: Xi Wang <xi.wang@gmail.com> Signed-off-by: Xi Wang <xi.wang@gmail.com> Signed-off-by: Luke Nelson <luke.r.nels@gmail.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Reviewed-by: Björn Töpel <bjorn.topel@gmail.com> Acked-by: Björn Töpel <bjorn.topel@gmail.com> Link: https://lore.kernel.org/bpf/20200305050207.4159-3-luke.r.nels@gmail.com		2020-03-05 16:13:47 +01:00
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boot	riscv: Fix gitignore	2020-02-19 16:13:51 -08:00
configs	Merge branch 'next/defconfig-add-debug' into for-next	2019-11-22 18:59:23 -08:00
include	riscv: set pmp configuration if kernel is running in M-mode	2020-02-18 09:41:24 -08:00
kernel	RISC-V: Don't enable all interrupts in trap_init()	2020-02-18 10:34:04 -08:00
lib	riscv: Add KASAN support	2020-01-22 13:09:58 -08:00
mm	riscv: adjust the indent	2020-02-24 13:12:53 -08:00
net	riscv, bpf: Add RV32G eBPF JIT	2020-03-05 16:13:47 +01:00
Kbuild	riscv: add arch/riscv/Kbuild	2019-08-30 17:34:00 -07:00
Kconfig	riscv, bpf: Add RV32G eBPF JIT	2020-03-05 16:13:47 +01:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.socs	riscv: only select serial sifive if TTY is enabled	2019-12-08 20:29:01 -08:00
Makefile	riscv: provide a flat image loader	2019-11-17 15:17:39 -08:00