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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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d467239f37
This adds the constants necessary to use the renesas,r9a06g032-sysctrl node. Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
149 lines
5.0 KiB
C
149 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* R9A06G032 sysctrl IDs
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*
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* Copyright (C) 2018 Renesas Electronics Europe Limited
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*
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* Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
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*/
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#ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__
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#define __DT_BINDINGS_R9A06G032_SYSCTRL_H__
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#define R9A06G032_CLK_PLL_USB 1
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#define R9A06G032_CLK_48 1 /* AKA CLK_PLL_USB */
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#define R9A06G032_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */
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#define R9A06G032_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */
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#define R9A06G032_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */
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#define R9A06G032_CLK50 6 /* AKA CLKOUT_D20 */
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#define R9A06G032_CLK25 7 /* AKA CLKOUT_D40 */
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#define R9A06G032_CLK125 9 /* AKA CLKOUT_D8 */
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#define R9A06G032_CLK_P5_PG1 17 /* AKA DIV_P5_PG */
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#define R9A06G032_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */
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#define R9A06G032_CLK_25_PG4 26
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#define R9A06G032_CLK_25_PG5 27
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#define R9A06G032_CLK_25_PG6 28
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#define R9A06G032_CLK_25_PG7 29
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#define R9A06G032_CLK_25_PG8 30
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#define R9A06G032_CLK_ADC 31
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#define R9A06G032_CLK_ECAT100 32
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#define R9A06G032_CLK_HSR100 33
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#define R9A06G032_CLK_I2C0 34
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#define R9A06G032_CLK_I2C1 35
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#define R9A06G032_CLK_MII_REF 36
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#define R9A06G032_CLK_NAND 37
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#define R9A06G032_CLK_NOUSBP2_PG6 38
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#define R9A06G032_CLK_P1_PG2 39
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#define R9A06G032_CLK_P1_PG3 40
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#define R9A06G032_CLK_P1_PG4 41
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#define R9A06G032_CLK_P4_PG3 42
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#define R9A06G032_CLK_P4_PG4 43
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#define R9A06G032_CLK_P6_PG1 44
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#define R9A06G032_CLK_P6_PG2 45
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#define R9A06G032_CLK_P6_PG3 46
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#define R9A06G032_CLK_P6_PG4 47
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#define R9A06G032_CLK_PCI_USB 48
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#define R9A06G032_CLK_QSPI0 49
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#define R9A06G032_CLK_QSPI1 50
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#define R9A06G032_CLK_RGMII_REF 51
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#define R9A06G032_CLK_RMII_REF 52
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#define R9A06G032_CLK_SDIO0 53
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#define R9A06G032_CLK_SDIO1 54
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#define R9A06G032_CLK_SERCOS100 55
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#define R9A06G032_CLK_SLCD 56
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#define R9A06G032_CLK_SPI0 57
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#define R9A06G032_CLK_SPI1 58
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#define R9A06G032_CLK_SPI2 59
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#define R9A06G032_CLK_SPI3 60
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#define R9A06G032_CLK_SPI4 61
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#define R9A06G032_CLK_SPI5 62
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#define R9A06G032_CLK_SWITCH 63
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#define R9A06G032_HCLK_ECAT125 65
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#define R9A06G032_HCLK_PINCONFIG 66
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#define R9A06G032_HCLK_SERCOS 67
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#define R9A06G032_HCLK_SGPIO2 68
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#define R9A06G032_HCLK_SGPIO3 69
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#define R9A06G032_HCLK_SGPIO4 70
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#define R9A06G032_HCLK_TIMER0 71
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#define R9A06G032_HCLK_TIMER1 72
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#define R9A06G032_HCLK_USBF 73
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#define R9A06G032_HCLK_USBH 74
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#define R9A06G032_HCLK_USBPM 75
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#define R9A06G032_CLK_48_PG_F 76
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#define R9A06G032_CLK_48_PG4 77
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#define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */
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#define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */
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#define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */
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#define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */
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#define R9A06G032_HCLK_CAN0 85
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#define R9A06G032_HCLK_CAN1 86
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#define R9A06G032_HCLK_DELTASIGMA 87
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#define R9A06G032_HCLK_PWMPTO 88
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#define R9A06G032_HCLK_RSV 89
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#define R9A06G032_HCLK_SGPIO0 90
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#define R9A06G032_HCLK_SGPIO1 91
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#define R9A06G032_RTOS_MDC 92
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#define R9A06G032_CLK_CM3 93
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#define R9A06G032_CLK_DDRC 94
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#define R9A06G032_CLK_ECAT25 95
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#define R9A06G032_CLK_HSR50 96
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#define R9A06G032_CLK_HW_RTOS 97
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#define R9A06G032_CLK_SERCOS50 98
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#define R9A06G032_HCLK_ADC 99
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#define R9A06G032_HCLK_CM3 100
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#define R9A06G032_HCLK_CRYPTO_EIP150 101
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#define R9A06G032_HCLK_CRYPTO_EIP93 102
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#define R9A06G032_HCLK_DDRC 103
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#define R9A06G032_HCLK_DMA0 104
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#define R9A06G032_HCLK_DMA1 105
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#define R9A06G032_HCLK_GMAC0 106
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#define R9A06G032_HCLK_GMAC1 107
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#define R9A06G032_HCLK_GPIO0 108
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#define R9A06G032_HCLK_GPIO1 109
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#define R9A06G032_HCLK_GPIO2 110
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#define R9A06G032_HCLK_HSR 111
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#define R9A06G032_HCLK_I2C0 112
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#define R9A06G032_HCLK_I2C1 113
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#define R9A06G032_HCLK_LCD 114
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#define R9A06G032_HCLK_MSEBI_M 115
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#define R9A06G032_HCLK_MSEBI_S 116
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#define R9A06G032_HCLK_NAND 117
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#define R9A06G032_HCLK_PG_I 118
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#define R9A06G032_HCLK_PG19 119
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#define R9A06G032_HCLK_PG20 120
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#define R9A06G032_HCLK_PG3 121
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#define R9A06G032_HCLK_PG4 122
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#define R9A06G032_HCLK_QSPI0 123
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#define R9A06G032_HCLK_QSPI1 124
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#define R9A06G032_HCLK_ROM 125
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#define R9A06G032_HCLK_RTC 126
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#define R9A06G032_HCLK_SDIO0 127
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#define R9A06G032_HCLK_SDIO1 128
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#define R9A06G032_HCLK_SEMAP 129
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#define R9A06G032_HCLK_SPI0 130
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#define R9A06G032_HCLK_SPI1 131
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#define R9A06G032_HCLK_SPI2 132
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#define R9A06G032_HCLK_SPI3 133
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#define R9A06G032_HCLK_SPI4 134
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#define R9A06G032_HCLK_SPI5 135
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#define R9A06G032_HCLK_SWITCH 136
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#define R9A06G032_HCLK_SWITCH_RG 137
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#define R9A06G032_HCLK_UART0 138
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#define R9A06G032_HCLK_UART1 139
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#define R9A06G032_HCLK_UART2 140
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#define R9A06G032_HCLK_UART3 141
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#define R9A06G032_HCLK_UART4 142
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#define R9A06G032_HCLK_UART5 143
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#define R9A06G032_HCLK_UART6 144
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#define R9A06G032_HCLK_UART7 145
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#define R9A06G032_CLK_UART0 146
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#define R9A06G032_CLK_UART1 147
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#define R9A06G032_CLK_UART2 148
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#define R9A06G032_CLK_UART3 149
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#define R9A06G032_CLK_UART4 150
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#define R9A06G032_CLK_UART5 151
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#define R9A06G032_CLK_UART6 152
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#define R9A06G032_CLK_UART7 153
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#endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */
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