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MPU DPLL on OMAP5, DRA75x, DRA72x has a limitation on the maximum frequency it can be locked at. Duty Cycle Correction circuit is used to recover a correct duty cycle for achieving higher frequencies (hardware internally switches output to M3 output(CLKOUTHIF) from M2 output (CLKOUT)). So provide support to setup required data to handle Duty cycle by the setting up the minimum frequency for DPLL. 1.4GHz is common for all these devices and is based on Technical Reference Manual information for OMAP5432((SWPU282U) chapter 3.6.3.3.1 "DPLLs Output Clocks Parameters", and equivalent information from DRA75x, DRA72x documentation(SPRUHP2E, SPRUHI2P). Signed-off-by: Nishanth Menon <nm@ti.com> [t-kristo@ti.com: updated for latest dpll init API call] Signed-off-by: Tero Kristo <t-kristo@ti.com>
86 lines
2.9 KiB
Plaintext
86 lines
2.9 KiB
Plaintext
Binding for Texas Instruments DPLL clock.
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Binding status: Unstable - ABI compatibility may be broken in the future
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This binding uses the common clock binding[1]. It assumes a
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register-mapped DPLL with usually two selectable input clocks
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(reference clock and bypass clock), with digital phase locked
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loop logic for multiplying the input clock to a desired output
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clock. This clock also typically supports different operation
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modes (locked, low power stop etc.) This binding has several
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sub-types, which effectively result in slightly different setup
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for the actual DPLL clock.
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be one of:
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"ti,omap3-dpll-clock",
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"ti,omap3-dpll-core-clock",
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"ti,omap3-dpll-per-clock",
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"ti,omap3-dpll-per-j-type-clock",
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"ti,omap4-dpll-clock",
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"ti,omap4-dpll-x2-clock",
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"ti,omap4-dpll-core-clock",
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"ti,omap4-dpll-m4xen-clock",
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"ti,omap4-dpll-j-type-clock",
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"ti,omap5-mpu-dpll-clock",
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"ti,am3-dpll-no-gate-clock",
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"ti,am3-dpll-j-type-clock",
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"ti,am3-dpll-no-gate-j-type-clock",
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"ti,am3-dpll-clock",
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"ti,am3-dpll-core-clock",
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"ti,am3-dpll-x2-clock",
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"ti,omap2-dpll-core-clock",
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- #clock-cells : from common clock binding; shall be set to 0.
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- clocks : link phandles of parent clocks, first entry lists reference clock
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and second entry bypass clock
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- reg : offsets for the register set for controlling the DPLL.
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Registers are listed in following order:
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"control" - contains the control register base address
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"idlest" - contains the idle status register base address
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"mult-div1" - contains the multiplier / divider register base address
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"autoidle" - contains the autoidle register base address (optional)
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ti,am3-* dpll types do not have autoidle register
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ti,omap2-* dpll type does not support idlest / autoidle registers
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Optional properties:
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- DPLL mode setting - defining any one or more of the following overrides
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default setting.
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- ti,low-power-stop : DPLL supports low power stop mode, gating output
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- ti,low-power-bypass : DPLL output matches rate of parent bypass clock
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- ti,lock : DPLL locks in programmed rate
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Examples:
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dpll_core_ck: dpll_core_ck@44e00490 {
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#clock-cells = <0>;
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compatible = "ti,omap4-dpll-core-clock";
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clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
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reg = <0x490>, <0x45c>, <0x488>, <0x468>;
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};
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dpll2_ck: dpll2_ck@48004004 {
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#clock-cells = <0>;
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compatible = "ti,omap3-dpll-clock";
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clocks = <&sys_ck>, <&dpll2_fck>;
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ti,low-power-stop;
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ti,low-power-bypass;
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ti,lock;
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reg = <0x4>, <0x24>, <0x34>, <0x40>;
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};
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dpll_core_ck: dpll_core_ck@44e00490 {
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#clock-cells = <0>;
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compatible = "ti,am3-dpll-core-clock";
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clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
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reg = <0x90>, <0x5c>, <0x68>;
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};
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dpll_ck: dpll_ck {
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#clock-cells = <0>;
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compatible = "ti,omap2-dpll-core-clock";
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clocks = <&sys_ck>, <&sys_ck>;
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reg = <0x0500>, <0x0540>;
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};
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