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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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acddfc2c26
Add MT8183 clock support, include topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
106 lines
2.6 KiB
C
106 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (c) 2018 MediaTek Inc.
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// Author: Weiyi Lu <weiyi.lu@mediatek.com>
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#include <linux/clk-provider.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt8183-clk.h>
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static const struct mtk_gate_regs audio0_cg_regs = {
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.set_ofs = 0x0,
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.clr_ofs = 0x0,
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.sta_ofs = 0x0,
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};
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static const struct mtk_gate_regs audio1_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x4,
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.sta_ofs = 0x4,
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};
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#define GATE_AUDIO0(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
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&mtk_clk_gate_ops_no_setclr)
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#define GATE_AUDIO1(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, \
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&mtk_clk_gate_ops_no_setclr)
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static const struct mtk_gate audio_clks[] = {
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/* AUDIO0 */
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GATE_AUDIO0(CLK_AUDIO_AFE, "aud_afe", "audio_sel",
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2),
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GATE_AUDIO0(CLK_AUDIO_22M, "aud_22m", "aud_eng1_sel",
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8),
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GATE_AUDIO0(CLK_AUDIO_24M, "aud_24m", "aud_eng2_sel",
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9),
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GATE_AUDIO0(CLK_AUDIO_APLL2_TUNER, "aud_apll2_tuner", "aud_eng2_sel",
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18),
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GATE_AUDIO0(CLK_AUDIO_APLL_TUNER, "aud_apll_tuner", "aud_eng1_sel",
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19),
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GATE_AUDIO0(CLK_AUDIO_TDM, "aud_tdm", "apll12_divb",
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20),
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GATE_AUDIO0(CLK_AUDIO_ADC, "aud_adc", "audio_sel",
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24),
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GATE_AUDIO0(CLK_AUDIO_DAC, "aud_dac", "audio_sel",
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25),
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GATE_AUDIO0(CLK_AUDIO_DAC_PREDIS, "aud_dac_predis", "audio_sel",
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26),
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GATE_AUDIO0(CLK_AUDIO_TML, "aud_tml", "audio_sel",
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27),
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/* AUDIO1 */
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GATE_AUDIO1(CLK_AUDIO_I2S1, "aud_i2s1", "audio_sel",
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4),
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GATE_AUDIO1(CLK_AUDIO_I2S2, "aud_i2s2", "audio_sel",
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5),
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GATE_AUDIO1(CLK_AUDIO_I2S3, "aud_i2s3", "audio_sel",
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6),
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GATE_AUDIO1(CLK_AUDIO_I2S4, "aud_i2s4", "audio_sel",
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7),
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GATE_AUDIO1(CLK_AUDIO_PDN_ADDA6_ADC, "aud_pdn_adda6_adc", "audio_sel",
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20),
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};
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static int clk_mt8183_audio_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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int r;
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struct device_node *node = pdev->dev.of_node;
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clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
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mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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return r;
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r = devm_of_platform_populate(&pdev->dev);
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if (r)
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of_clk_del_provider(node);
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return r;
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}
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static const struct of_device_id of_match_clk_mt8183_audio[] = {
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{ .compatible = "mediatek,mt8183-audiosys", },
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{}
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};
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static struct platform_driver clk_mt8183_audio_drv = {
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.probe = clk_mt8183_audio_probe,
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.driver = {
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.name = "clk-mt8183-audio",
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.of_match_table = of_match_clk_mt8183_audio,
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},
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};
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builtin_platform_driver(clk_mt8183_audio_drv);
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