mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 03:50:54 +07:00
3b93fc0f2a
On Exynos5422 and Exynos5800 we support 12 cpufreq steps (200-1300 MHz) for LITTLE and 18 steps for big core (200-1700 MHz). Add respective cooling cells. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
126 lines
3.5 KiB
Plaintext
126 lines
3.5 KiB
Plaintext
/*
|
|
* SAMSUNG EXYNOS5422 SoC cpu device tree source
|
|
*
|
|
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
|
|
* http://www.samsung.com
|
|
*
|
|
* This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
|
|
*
|
|
* The Exynos5420, 5422 and 5800 actually share the same CPU configuration
|
|
* but particular boards choose different booting order.
|
|
*
|
|
* Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
|
|
* booting cluster (big or LITTLE) is chosen by IROM code by reading
|
|
* the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
|
|
* from the LITTLE: Cortex-A7.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
/ {
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu0: cpu@100 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x100>;
|
|
clocks = <&clock CLK_KFC_CLK>;
|
|
clock-frequency = <1000000000>;
|
|
cci-control-port = <&cci_control0>;
|
|
operating-points-v2 = <&cluster_a7_opp_table>;
|
|
cooling-min-level = <0>;
|
|
cooling-max-level = <11>;
|
|
#cooling-cells = <2>; /* min followed by max */
|
|
};
|
|
|
|
cpu1: cpu@101 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x101>;
|
|
clock-frequency = <1000000000>;
|
|
cci-control-port = <&cci_control0>;
|
|
operating-points-v2 = <&cluster_a7_opp_table>;
|
|
cooling-min-level = <0>;
|
|
cooling-max-level = <11>;
|
|
#cooling-cells = <2>; /* min followed by max */
|
|
};
|
|
|
|
cpu2: cpu@102 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x102>;
|
|
clock-frequency = <1000000000>;
|
|
cci-control-port = <&cci_control0>;
|
|
operating-points-v2 = <&cluster_a7_opp_table>;
|
|
cooling-min-level = <0>;
|
|
cooling-max-level = <11>;
|
|
#cooling-cells = <2>; /* min followed by max */
|
|
};
|
|
|
|
cpu3: cpu@103 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x103>;
|
|
clock-frequency = <1000000000>;
|
|
cci-control-port = <&cci_control0>;
|
|
operating-points-v2 = <&cluster_a7_opp_table>;
|
|
cooling-min-level = <0>;
|
|
cooling-max-level = <11>;
|
|
#cooling-cells = <2>; /* min followed by max */
|
|
};
|
|
|
|
cpu4: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
clocks = <&clock CLK_ARM_CLK>;
|
|
reg = <0x0>;
|
|
clock-frequency = <1800000000>;
|
|
cci-control-port = <&cci_control1>;
|
|
operating-points-v2 = <&cluster_a15_opp_table>;
|
|
cooling-min-level = <0>;
|
|
cooling-max-level = <15>;
|
|
#cooling-cells = <2>; /* min followed by max */
|
|
};
|
|
|
|
cpu5: cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <0x1>;
|
|
clock-frequency = <1800000000>;
|
|
cci-control-port = <&cci_control1>;
|
|
operating-points-v2 = <&cluster_a15_opp_table>;
|
|
cooling-min-level = <0>;
|
|
cooling-max-level = <15>;
|
|
#cooling-cells = <2>; /* min followed by max */
|
|
};
|
|
|
|
cpu6: cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <0x2>;
|
|
clock-frequency = <1800000000>;
|
|
cci-control-port = <&cci_control1>;
|
|
operating-points-v2 = <&cluster_a15_opp_table>;
|
|
cooling-min-level = <0>;
|
|
cooling-max-level = <15>;
|
|
#cooling-cells = <2>; /* min followed by max */
|
|
};
|
|
|
|
cpu7: cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <0x3>;
|
|
clock-frequency = <1800000000>;
|
|
cci-control-port = <&cci_control1>;
|
|
operating-points-v2 = <&cluster_a15_opp_table>;
|
|
cooling-min-level = <0>;
|
|
cooling-max-level = <15>;
|
|
#cooling-cells = <2>; /* min followed by max */
|
|
};
|
|
};
|
|
};
|