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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a63141e317
Commit b0f3cd3191 ("drm/amdgpu: remove unnecessary JPEG2.0 code from
VCN2.0") introduced a new clang warning in the vcn_v2_0_stop function:
../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1082:2: warning: variable 'r'
is used uninitialized whenever 'while' loop exits because its condition
is false [-Wsometimes-uninitialized]
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../drivers/gpu/drm/amd/amdgpu/../amdgpu/soc15_common.h:55:10: note:
expanded from macro 'SOC15_WAIT_ON_RREG'
while ((tmp_ & (mask)) != (expected_value)) { \
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1083:6: note: uninitialized use
occurs here
if (r)
^
../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1082:2: note: remove the
condition if it is always true
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
^
../drivers/gpu/drm/amd/amdgpu/../amdgpu/soc15_common.h:55:10: note:
expanded from macro 'SOC15_WAIT_ON_RREG'
while ((tmp_ & (mask)) != (expected_value)) { \
^
../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1072:7: note: initialize the
variable 'r' to silence this warning
int r;
^
= 0
1 warning generated.
To prevent warnings like this from happening in the future, make the
SOC15_WAIT_ON_RREG macro initialize its ret variable before the while
loop that can time out. This macro's return value is always checked so
it should set ret in both the success and fail path.
Link: https://github.com/ClangBuiltLinux/linux/issues/776
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
131 lines
5.2 KiB
C
131 lines
5.2 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __SOC15_COMMON_H__
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#define __SOC15_COMMON_H__
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/* Register Access Macros */
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#define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
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#define WREG32_FIELD15(ip, idx, reg, field, val) \
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WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
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(RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
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& ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
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#define RREG32_SOC15(ip, inst, reg) \
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RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
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#define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
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RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)
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#define WREG32_SOC15(ip, inst, reg, value) \
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WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
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#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
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WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
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#define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
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WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)
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#define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask, ret) \
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do { \
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uint32_t old_ = 0; \
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uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
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uint32_t loop = adev->usec_timeout; \
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ret = 0; \
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while ((tmp_ & (mask)) != (expected_value)) { \
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if (old_ != tmp_) { \
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loop = adev->usec_timeout; \
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old_ = tmp_; \
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} else \
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udelay(1); \
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tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
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loop--; \
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if (!loop) { \
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DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n", \
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inst, #reg, (unsigned)expected_value, (unsigned)(tmp_ & (mask))); \
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ret = -ETIMEDOUT; \
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break; \
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} \
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} \
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} while (0)
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#define AMDGPU_VIRT_SUPPORT_RLC_PRG_REG(a) (amdgpu_sriov_vf((a)) && !amdgpu_sriov_runtime((a)))
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#define WREG32_RLC(reg, value) \
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do { \
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if (AMDGPU_VIRT_SUPPORT_RLC_PRG_REG(adev)) { \
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uint32_t i = 0; \
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uint32_t retries = 50000; \
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uint32_t r0 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0; \
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uint32_t r1 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1; \
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uint32_t spare_int = adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT; \
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WREG32(r0, value); \
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WREG32(r1, (reg | 0x80000000)); \
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WREG32(spare_int, 0x1); \
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for (i = 0; i < retries; i++) { \
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u32 tmp = RREG32(r1); \
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if (!(tmp & 0x80000000)) \
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break; \
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udelay(10); \
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} \
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if (i >= retries) \
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pr_err("timeout: rlcg program reg:0x%05x failed !\n", reg); \
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} else { \
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WREG32(reg, value); \
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} \
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} while (0)
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#define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \
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do { \
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uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
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if (AMDGPU_VIRT_SUPPORT_RLC_PRG_REG(adev)) { \
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uint32_t r2 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2; \
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uint32_t r3 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3; \
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uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; \
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uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; \
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if (target_reg == grbm_cntl) \
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WREG32(r2, value); \
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else if (target_reg == grbm_idx) \
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WREG32(r3, value); \
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WREG32(target_reg, value); \
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} else { \
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WREG32(target_reg, value); \
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} \
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} while (0)
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#define WREG32_SOC15_RLC(ip, inst, reg, value) \
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do { \
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uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\
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WREG32_RLC(target_reg, value); \
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} while (0)
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#define WREG32_FIELD15_RLC(ip, idx, reg, field, val) \
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WREG32_RLC((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
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(RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
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& ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
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#define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \
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WREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset), value)
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#endif
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