Hawking Zhang 5e62db9df6 drm/amdgpu: read sdma edc counter to clear the counters ... SDMA edc counter registers were added in gfx edc counters array. When querying gfx error counter in that array, there is no way to differentiate sdma instance number for different asic and then results to NULL pointer access when trying to read sdma register base address for instances greater than 2 on Vega20. In addition, this also results to wrong gfx error counters since it actually added sdma edc counters. Therefore, sdma edc counter registers should be separated from gfx edc counter regsiter array and only get initialized when driver tries to enable sdma ras. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-01-14 10:18:08 -05:00
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acp	drm/amdgpu: fix license on Kconfig and Makefiles	2019-12-11 15:22:08 -05:00
amdgpu	drm/amdgpu: read sdma edc counter to clear the counters	2020-01-14 10:18:08 -05:00
amdkfd	drm/amdkfd: Improve kfd_process lookup in kfd_ioctl	2020-01-09 16:08:19 -05:00
display	drm/amdgpu/display: Use u64 divide macro for round up division	2020-01-14 10:16:43 -05:00
include	drm/amdgpu: update the method to get fb_loc of memory training(V4)	2019-12-23 14:59:20 -05:00
powerplay	drm/amd/powerplay: cleanup the interfaces for powergate setting through SMU	2020-01-07 12:01:54 -05:00