Mark Yao 5e3bc6d1ab drm/rockchip: dw_hdmi: introduce the VPLL clock setting ... For RK3399 HDMI, there is an external clock need for HDMI PHY, and it should keep the same clock rate with VOP DCLK. VPLL have supported the clock for HDMI PHY, but there is no clock divider bewteen VPLL and HDMI PHY. So we need to set the VPLL rate manually in HDMI driver. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Mark Yao <mark.yao@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org>		2017-06-23 08:52:03 +08:00
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drm	drm/rockchip: dw_hdmi: introduce the VPLL clock setting	2017-06-23 08:52:03 +08:00
host1x	gpu: host1x: select IOMMU_IOVA	2017-05-18 10:17:43 -04:00
ipu-v3	gpu: ipu-v3: don't depend on DRM being enabled	2017-04-04 10:58:56 +02:00
vga	Pointer for Markus's image conversion work.	2017-03-14 15:07:33 +01:00
Makefile