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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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72350b29a4
Some OMAP2/3 hardware modules have CM_IDLEST attributes that are not handled by the current omap2_wait_clock_ready() code. In preparation for patches that fix the unusual devices, rename the function omap2_wait_clock_ready() to omap2_wait_module_ready() and split it into three parts: 1. A clkops-specific companion clock return function (by default, omap2_clk_dflt_find_companion()) 2. A clkops-specific CM_IDLEST register address and bit shift return function (by default, omap2_clk_dflt_find_idlest()) 3. Code to wait for the CM to indicate that the module is ready (omap2_cm_wait_idlest()) Clocks can now specify their own custom find_companion() and find_idlest() functions; used in subsequent patches. Signed-off-by: Paul Walmsley <paul@pwsan.com>
171 lines
4.1 KiB
C
171 lines
4.1 KiB
C
/*
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* linux/arch/arm/mach-omap2/prcm.c
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*
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* OMAP 24xx Power Reset and Clock Management (PRCM) functions
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*
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* Copyright (C) 2005 Nokia Corporation
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*
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* Written by Tony Lindgren <tony.lindgren@nokia.com>
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*
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* Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <mach/common.h>
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#include <mach/prcm.h>
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#include "clock.h"
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#include "prm.h"
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#include "prm-regbits-24xx.h"
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static void __iomem *prm_base;
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static void __iomem *cm_base;
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#define MAX_MODULE_ENABLE_WAIT 100000
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u32 omap_prcm_get_reset_sources(void)
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{
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/* XXX This presumably needs modification for 34XX */
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return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f;
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}
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EXPORT_SYMBOL(omap_prcm_get_reset_sources);
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/* Resets clock rates and reboots the system. Only called from system.h */
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void omap_prcm_arch_reset(char mode)
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{
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s16 prcm_offs;
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omap2_clk_prepare_for_reboot();
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if (cpu_is_omap24xx())
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prcm_offs = WKUP_MOD;
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else if (cpu_is_omap34xx())
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prcm_offs = OMAP3430_GR_MOD;
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else
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WARN_ON(1);
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prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL);
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}
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static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
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{
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BUG_ON(!base);
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return __raw_readl(base + module + reg);
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}
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static inline void __omap_prcm_write(u32 value, void __iomem *base,
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s16 module, u16 reg)
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{
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BUG_ON(!base);
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__raw_writel(value, base + module + reg);
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}
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/* Read a register in a PRM module */
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u32 prm_read_mod_reg(s16 module, u16 idx)
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{
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return __omap_prcm_read(prm_base, module, idx);
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}
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EXPORT_SYMBOL(prm_read_mod_reg);
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/* Write into a register in a PRM module */
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void prm_write_mod_reg(u32 val, s16 module, u16 idx)
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{
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__omap_prcm_write(val, prm_base, module, idx);
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}
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EXPORT_SYMBOL(prm_write_mod_reg);
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/* Read-modify-write a register in a PRM module. Caller must lock */
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u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
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{
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u32 v;
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v = prm_read_mod_reg(module, idx);
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v &= ~mask;
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v |= bits;
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prm_write_mod_reg(v, module, idx);
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return v;
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}
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EXPORT_SYMBOL(prm_rmw_mod_reg_bits);
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/* Read a register in a CM module */
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u32 cm_read_mod_reg(s16 module, u16 idx)
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{
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return __omap_prcm_read(cm_base, module, idx);
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}
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EXPORT_SYMBOL(cm_read_mod_reg);
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/* Write into a register in a CM module */
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void cm_write_mod_reg(u32 val, s16 module, u16 idx)
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{
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__omap_prcm_write(val, cm_base, module, idx);
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}
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EXPORT_SYMBOL(cm_write_mod_reg);
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/* Read-modify-write a register in a CM module. Caller must lock */
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u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
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{
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u32 v;
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v = cm_read_mod_reg(module, idx);
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v &= ~mask;
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v |= bits;
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cm_write_mod_reg(v, module, idx);
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return v;
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}
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EXPORT_SYMBOL(cm_rmw_mod_reg_bits);
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/**
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* omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
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* @reg: physical address of module IDLEST register
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* @mask: value to mask against to determine if the module is active
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* @name: name of the clock (for printk)
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*
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* Returns 1 if the module indicated readiness in time, or 0 if it
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* failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
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*/
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int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
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{
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int i = 0;
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int ena = 0;
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/*
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* 24xx uses 0 to indicate not ready, and 1 to indicate ready.
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* 34xx reverses this, just to keep us on our toes
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*/
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if (cpu_is_omap24xx())
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ena = mask;
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else if (cpu_is_omap34xx())
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ena = 0;
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else
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BUG();
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/* Wait for lock */
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while (((__raw_readl(reg) & mask) != ena) &&
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(i++ < MAX_MODULE_ENABLE_WAIT))
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udelay(1);
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if (i < MAX_MODULE_ENABLE_WAIT)
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pr_debug("cm: Module associated with clock %s ready after %d "
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"loops\n", name, i);
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else
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pr_err("cm: Module associated with clock %s didn't enable in "
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"%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
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return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
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};
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void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
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{
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prm_base = omap2_globals->prm;
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cm_base = omap2_globals->cm;
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}
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