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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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11f8e119ed
The Amlogic Meson GXM SoC embeds an ARM Mali T820 GPU. This patch adds the node with all the needed properties to power on the GPU. This has been tested with the work-in-progress PanFrost project aiming support for ARM Mali Midgard and later GPUs. Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
147 lines
3.0 KiB
Plaintext
147 lines
3.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2016 Endless Computers, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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*/
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#include "meson-gxl.dtsi"
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/ {
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compatible = "amlogic,meson-gxm";
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cpus {
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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core2 {
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cpu = <&cpu6>;
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};
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core3 {
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cpu = <&cpu7>;
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};
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};
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};
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cpu4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x100>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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clocks = <&scpi_dvfs 1>;
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};
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cpu5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x101>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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clocks = <&scpi_dvfs 1>;
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};
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cpu6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x102>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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clocks = <&scpi_dvfs 1>;
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};
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cpu7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x103>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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clocks = <&scpi_dvfs 1>;
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};
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};
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};
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&apb {
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usb2_phy2: phy@78040 {
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compatible = "amlogic,meson-gxl-usb2-phy";
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#phy-cells = <0>;
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reg = <0x0 0x78040 0x0 0x20>;
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clocks = <&clkc CLKID_USB>;
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clock-names = "phy";
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resets = <&reset RESET_USB_OTG>;
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reset-names = "phy";
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status = "okay";
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};
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mali: gpu@c0000 {
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compatible = "amlogic,meson-gxm-mali", "arm,mali-t820";
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reg = <0x0 0xc0000 0x0 0x40000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gpu", "mmu", "job";
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clocks = <&clkc CLKID_MALI>;
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resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>;
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/*
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* Mali clocking is provided by two identical clock paths
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* MALI_0 and MALI_1 muxed to a single clock by a glitch
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* free mux to safely change frequency while running.
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*/
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assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
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<&clkc CLKID_MALI_0>,
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<&clkc CLKID_MALI>; /* Glitch free mux */
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assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
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<0>, /* Do Nothing */
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<&clkc CLKID_MALI_0>;
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assigned-clock-rates = <0>, /* Do Nothing */
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<666666666>,
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<0>; /* Do Nothing */
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};
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};
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&clkc_AO {
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compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc";
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};
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&saradc {
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compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc";
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};
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&scpi_dvfs {
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clock-indices = <0 1>;
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clock-output-names = "vbig", "vlittle";
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};
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&vpu {
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compatible = "amlogic,meson-gxm-vpu", "amlogic,meson-gx-vpu";
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};
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&hdmi_tx {
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compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
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};
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&dwc3 {
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phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>;
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};
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