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d584a10d1e
The 98DX4122 dtsi file lacks the defintion of the PCIe controller which is present on this SoC. The SATA phys must also be explicitely disabled since they are not present on this SoC. If they remain enabled, a hardlock occures when their clock gates are enabled. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Link: https://lkml.kernel.org/r/1400230143-15620-2-git-send-email-valentin.longchamp@keymile.com Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
52 lines
1.1 KiB
Plaintext
52 lines
1.1 KiB
Plaintext
/ {
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mbus {
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pciec: pcie-controller {
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compatible = "marvell,kirkwood-pcie";
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status = "disabled";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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ranges =
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<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
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0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
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0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
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pcie0: pcie@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
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0x81000000 0 0 0x81000000 0x1 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &intc 9>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
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clocks = <&gate_clk 2>;
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status = "disabled";
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};
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};
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};
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ocp@f1000000 {
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pinctrl: pin-controller@10000 {
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compatible = "marvell,98dx4122-pinctrl";
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};
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};
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};
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&sata_phy0 {
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status = "disabled";
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};
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&sata_phy1 {
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status = "disabled";
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};
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