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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a4c3733d32
Many of the privileged CSRs exist in a supervisor and machine version that are used very similarly. Provide versions of the CSR names and fields that map to either the S-mode or M-mode variant depending on a new CONFIG_RISCV_M_MODE kconfig symbol. Contains contributions from Damien Le Moal <Damien.LeMoal@wdc.com> and Paul Walmsley <paul.walmsley@sifive.com>. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> # for drivers/clocksource, drivers/irqchip [paul.walmsley@sifive.com: updated to apply] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
56 lines
1.1 KiB
C
56 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_IRQFLAGS_H
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#define _ASM_RISCV_IRQFLAGS_H
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#include <asm/processor.h>
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#include <asm/csr.h>
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/* read interrupt enabled status */
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static inline unsigned long arch_local_save_flags(void)
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{
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return csr_read(CSR_STATUS);
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}
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/* unconditionally enable interrupts */
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static inline void arch_local_irq_enable(void)
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{
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csr_set(CSR_STATUS, SR_IE);
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}
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/* unconditionally disable interrupts */
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static inline void arch_local_irq_disable(void)
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{
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csr_clear(CSR_STATUS, SR_IE);
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}
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/* get status and disable interrupts */
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static inline unsigned long arch_local_irq_save(void)
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{
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return csr_read_clear(CSR_STATUS, SR_IE);
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}
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/* test flags */
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static inline int arch_irqs_disabled_flags(unsigned long flags)
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{
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return !(flags & SR_IE);
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}
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/* test hardware interrupt enable bit */
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static inline int arch_irqs_disabled(void)
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{
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return arch_irqs_disabled_flags(arch_local_save_flags());
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}
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/* set interrupt enabled status */
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static inline void arch_local_irq_restore(unsigned long flags)
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{
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csr_set(CSR_STATUS, flags & SR_IE);
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}
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#endif /* _ASM_RISCV_IRQFLAGS_H */
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