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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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38f5bd23de
There are no standard CSR registers to provide cache information, the way for RISC-V is to get this information from DT. Currently, AT_L1I_X, AT_L1D_X and AT_L2_X are present in glibc header, and sysconf syscall could use them to get information of cache through AUX vector. The result of 'getconf -a' as follows: LEVEL1_ICACHE_SIZE 32768 LEVEL1_ICACHE_ASSOC 8 LEVEL1_ICACHE_LINESIZE 64 LEVEL1_DCACHE_SIZE 32768 LEVEL1_DCACHE_ASSOC 8 LEVEL1_DCACHE_LINESIZE 64 LEVEL2_CACHE_SIZE 2097152 LEVEL2_CACHE_ASSOC 32 LEVEL2_CACHE_LINESIZE 64 Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Pekka Enberg <penberg@kernel.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
85 lines
2.4 KiB
C
85 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
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* Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
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* Copyright (C) 2012 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_ELF_H
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#define _ASM_RISCV_ELF_H
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#include <uapi/asm/elf.h>
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#include <asm/auxvec.h>
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#include <asm/byteorder.h>
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#include <asm/cacheinfo.h>
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/*
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* These are used to set parameters in the core dumps.
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*/
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#define ELF_ARCH EM_RISCV
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#ifdef CONFIG_64BIT
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#define ELF_CLASS ELFCLASS64
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#else
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#define ELF_CLASS ELFCLASS32
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#endif
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#define ELF_DATA ELFDATA2LSB
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/*
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* This is used to ensure we don't load something for the wrong architecture.
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*/
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#define elf_check_arch(x) ((x)->e_machine == EM_RISCV)
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#define CORE_DUMP_USE_REGSET
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#define ELF_EXEC_PAGESIZE (PAGE_SIZE)
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/*
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* This is the location that an ET_DYN program is loaded if exec'ed. Typical
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* use of this is to invoke "./ld.so someprog" to test out a new version of
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* the loader. We need to make sure that it is out of the way of the program
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* that it will "exec", and that there is sufficient room for the brk.
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*/
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#define ELF_ET_DYN_BASE ((TASK_SIZE / 3) * 2)
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/*
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* This yields a mask that user programs can use to figure out what
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* instruction set this CPU supports. This could be done in user space,
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* but it's not easy, and we've already done it here.
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*/
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#define ELF_HWCAP (elf_hwcap)
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extern unsigned long elf_hwcap;
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/*
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* This yields a string that ld.so will use to load implementation
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* specific libraries for optimization. This is more specific in
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* intent than poking at uname or /proc/cpuinfo.
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*/
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#define ELF_PLATFORM (NULL)
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#ifdef CONFIG_MMU
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#define ARCH_DLINFO \
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do { \
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NEW_AUX_ENT(AT_SYSINFO_EHDR, \
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(elf_addr_t)current->mm->context.vdso); \
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NEW_AUX_ENT(AT_L1I_CACHESIZE, \
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get_cache_size(1, CACHE_TYPE_INST)); \
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NEW_AUX_ENT(AT_L1I_CACHEGEOMETRY, \
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get_cache_geometry(1, CACHE_TYPE_INST)); \
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NEW_AUX_ENT(AT_L1D_CACHESIZE, \
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get_cache_size(1, CACHE_TYPE_DATA)); \
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NEW_AUX_ENT(AT_L1D_CACHEGEOMETRY, \
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get_cache_geometry(1, CACHE_TYPE_DATA)); \
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NEW_AUX_ENT(AT_L2_CACHESIZE, \
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get_cache_size(2, CACHE_TYPE_UNIFIED)); \
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NEW_AUX_ENT(AT_L2_CACHEGEOMETRY, \
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get_cache_geometry(2, CACHE_TYPE_UNIFIED)); \
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} while (0)
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#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
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struct linux_binprm;
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extern int arch_setup_additional_pages(struct linux_binprm *bprm,
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int uses_interp);
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#endif /* CONFIG_MMU */
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#endif /* _ASM_RISCV_ELF_H */
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