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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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26de4f1b2f
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Simon Horman <horms@verge.net.au> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
143 lines
4.2 KiB
C
143 lines
4.2 KiB
C
#ifndef __LINUX_SERIAL_SCI_H
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#define __LINUX_SERIAL_SCI_H
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#include <linux/serial_core.h>
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#include <linux/sh_dma.h>
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/*
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* Generic header for SuperH (H)SCI(F) (used by sh/sh64 and related parts)
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*/
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#define SCIx_NOT_SUPPORTED (-1)
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/* SCSMR (Serial Mode Register) */
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#define SCSMR_CHR (1 << 6) /* 7-bit Character Length */
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#define SCSMR_PE (1 << 5) /* Parity Enable */
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#define SCSMR_ODD (1 << 4) /* Odd Parity */
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#define SCSMR_STOP (1 << 3) /* Stop Bit Length */
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#define SCSMR_CKS 0x0003 /* Clock Select */
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/* Serial Control Register (@ = not supported by all parts) */
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#define SCSCR_TIE (1 << 7) /* Transmit Interrupt Enable */
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#define SCSCR_RIE (1 << 6) /* Receive Interrupt Enable */
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#define SCSCR_TE (1 << 5) /* Transmit Enable */
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#define SCSCR_RE (1 << 4) /* Receive Enable */
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#define SCSCR_REIE (1 << 3) /* Receive Error Interrupt Enable @ */
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#define SCSCR_TOIE (1 << 2) /* Timeout Interrupt Enable @ */
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#define SCSCR_CKE1 (1 << 1) /* Clock Enable 1 */
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#define SCSCR_CKE0 (1 << 0) /* Clock Enable 0 */
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/* SCIFA/SCIFB only */
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#define SCSCR_TDRQE (1 << 15) /* Tx Data Transfer Request Enable */
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#define SCSCR_RDRQE (1 << 14) /* Rx Data Transfer Request Enable */
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/* SCxSR (Serial Status Register) on SCI */
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#define SCI_TDRE 0x80 /* Transmit Data Register Empty */
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#define SCI_RDRF 0x40 /* Receive Data Register Full */
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#define SCI_ORER 0x20 /* Overrun Error */
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#define SCI_FER 0x10 /* Framing Error */
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#define SCI_PER 0x08 /* Parity Error */
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#define SCI_TEND 0x04 /* Transmit End */
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#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
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/* SCxSR (Serial Status Register) on SCIF, HSCIF */
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#define SCIF_ER 0x0080 /* Receive Error */
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#define SCIF_TEND 0x0040 /* Transmission End */
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#define SCIF_TDFE 0x0020 /* Transmit FIFO Data Empty */
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#define SCIF_BRK 0x0010 /* Break Detect */
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#define SCIF_FER 0x0008 /* Framing Error */
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#define SCIF_PER 0x0004 /* Parity Error */
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#define SCIF_RDF 0x0002 /* Receive FIFO Data Full */
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#define SCIF_DR 0x0001 /* Receive Data Ready */
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#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
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/* SCFCR (FIFO Control Register) */
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#define SCFCR_LOOP (1 << 0) /* Loopback Test */
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/* SCSPTR (Serial Port Register), optional */
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#define SCSPTR_RTSIO (1 << 7) /* Serial Port RTS Pin Input/Output */
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#define SCSPTR_CTSIO (1 << 5) /* Serial Port CTS Pin Input/Output */
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#define SCSPTR_SPB2IO (1 << 1) /* Serial Port Break Input/Output */
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#define SCSPTR_SPB2DT (1 << 0) /* Serial Port Break Data */
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/* HSSRR HSCIF */
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#define HSCIF_SRE 0x8000 /* Sampling Rate Register Enable */
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enum {
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SCIx_PROBE_REGTYPE,
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SCIx_SCI_REGTYPE,
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SCIx_IRDA_REGTYPE,
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SCIx_SCIFA_REGTYPE,
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SCIx_SCIFB_REGTYPE,
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SCIx_SH2_SCIF_FIFODATA_REGTYPE,
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SCIx_SH3_SCIF_REGTYPE,
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SCIx_SH4_SCIF_REGTYPE,
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SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
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SCIx_SH4_SCIF_FIFODATA_REGTYPE,
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SCIx_SH7705_SCIF_REGTYPE,
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SCIx_HSCIF_REGTYPE,
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SCIx_NR_REGTYPES,
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};
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/*
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* SCI register subset common for all port types.
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* Not all registers will exist on all parts.
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*/
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enum {
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SCSMR, /* Serial Mode Register */
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SCBRR, /* Bit Rate Register */
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SCSCR, /* Serial Control Register */
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SCxSR, /* Serial Status Register */
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SCFCR, /* FIFO Control Register */
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SCFDR, /* FIFO Data Count Register */
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SCxTDR, /* Transmit (FIFO) Data Register */
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SCxRDR, /* Receive (FIFO) Data Register */
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SCLSR, /* Line Status Register */
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SCTFDR, /* Transmit FIFO Data Count Register */
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SCRFDR, /* Receive FIFO Data Count Register */
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SCSPTR, /* Serial Port Register */
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HSSRR, /* Sampling Rate Register */
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SCIx_NR_REGS,
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};
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struct device;
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struct plat_sci_port_ops {
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void (*init_pins)(struct uart_port *, unsigned int cflag);
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};
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/*
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* Port-specific capabilities
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*/
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#define SCIx_HAVE_RTSCTS (1 << 0)
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/*
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* Platform device specific platform_data struct
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*/
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struct plat_sci_port {
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unsigned int type; /* SCI / SCIF / IRDA / HSCIF */
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upf_t flags; /* UPF_* flags */
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unsigned long capabilities; /* Port features/capabilities */
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unsigned int sampling_rate;
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unsigned int scscr; /* SCSCR initialization */
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/*
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* Platform overrides if necessary, defaults otherwise.
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*/
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int port_reg;
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unsigned char regshift;
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unsigned char regtype;
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struct plat_sci_port_ops *ops;
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unsigned int dma_slave_tx;
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unsigned int dma_slave_rx;
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};
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#endif /* __LINUX_SERIAL_SCI_H */
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