mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
5d1190ea69
This commit migrates the mach-orion5x platforms to use the mvebu-mbus driver and therefore removes the Orion5x-specific addr-map code. The dove_init_early() function now initializes the mvebu-mbus driver by calling mvebu_mbus_init(). We also convert a number of orion5x_setup_xyz_win() calls to the appropriate mvebu_mbus_add_window() calls, as each board was doing its own setup for the NOR window or other devices. Ultimately, those devices will be probed from the DT. The common address decoding windows are now registered in the orion5x_setup_wins() function. It is worth noting that the four PCIe address decoding windows will ultimately no longer have to be registered here: it will be done automatically by the PCIe driver once Dove has been migrated to use the upcoming mvebu PCIe driver. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
384 lines
11 KiB
C
384 lines
11 KiB
C
/*
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* arch/arm/mach-orion5x/common.c
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*
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* Core functions for Marvell Orion 5x SoCs
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/serial_8250.h>
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#include <linux/mv643xx_i2c.h>
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#include <linux/ata_platform.h>
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#include <linux/delay.h>
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#include <linux/clk-provider.h>
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#include <net/dsa.h>
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#include <asm/page.h>
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#include <asm/setup.h>
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#include <asm/system_misc.h>
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#include <asm/timex.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <mach/bridge-regs.h>
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#include <mach/hardware.h>
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#include <mach/orion5x.h>
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#include <linux/platform_data/mtd-orion_nand.h>
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#include <linux/platform_data/usb-ehci-orion.h>
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#include <plat/time.h>
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#include <plat/common.h>
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#include "common.h"
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/*****************************************************************************
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* I/O Address Mapping
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****************************************************************************/
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static struct map_desc orion5x_io_desc[] __initdata = {
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{
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.virtual = (unsigned long) ORION5X_REGS_VIRT_BASE,
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.pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
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.length = ORION5X_REGS_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE,
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.pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
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.length = ORION5X_PCIE_WA_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init orion5x_map_io(void)
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{
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iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
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}
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/*****************************************************************************
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* CLK tree
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****************************************************************************/
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static struct clk *tclk;
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void __init clk_init(void)
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{
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tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
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orion5x_tclk);
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orion_clkdev_init(tclk);
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}
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/*****************************************************************************
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* EHCI0
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****************************************************************************/
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void __init orion5x_ehci0_init(void)
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{
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orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
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EHCI_PHY_ORION);
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}
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/*****************************************************************************
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* EHCI1
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****************************************************************************/
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void __init orion5x_ehci1_init(void)
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{
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orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
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}
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/*****************************************************************************
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* GE00
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****************************************************************************/
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void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
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{
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orion_ge00_init(eth_data,
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ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
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IRQ_ORION5X_ETH_ERR,
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MV643XX_TX_CSUM_DEFAULT_LIMIT);
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}
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/*****************************************************************************
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* Ethernet switch
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****************************************************************************/
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void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
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{
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orion_ge00_switch_init(d, irq);
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}
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/*****************************************************************************
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* I2C
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****************************************************************************/
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void __init orion5x_i2c_init(void)
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{
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orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
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}
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/*****************************************************************************
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* SATA
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****************************************************************************/
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void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
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{
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orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
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}
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/*****************************************************************************
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* SPI
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****************************************************************************/
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void __init orion5x_spi_init()
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{
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orion_spi_init(SPI_PHYS_BASE);
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}
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/*****************************************************************************
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* UART0
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****************************************************************************/
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void __init orion5x_uart0_init(void)
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{
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orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
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IRQ_ORION5X_UART0, tclk);
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}
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/*****************************************************************************
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* UART1
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****************************************************************************/
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void __init orion5x_uart1_init(void)
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{
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orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
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IRQ_ORION5X_UART1, tclk);
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}
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/*****************************************************************************
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* XOR engine
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****************************************************************************/
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void __init orion5x_xor_init(void)
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{
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orion_xor0_init(ORION5X_XOR_PHYS_BASE,
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ORION5X_XOR_PHYS_BASE + 0x200,
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IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
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}
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/*****************************************************************************
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* Cryptographic Engines and Security Accelerator (CESA)
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****************************************************************************/
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static void __init orion5x_crypto_init(void)
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{
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mvebu_mbus_add_window("sram", ORION5X_SRAM_PHYS_BASE,
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ORION5X_SRAM_SIZE);
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orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
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SZ_8K, IRQ_ORION5X_CESA);
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}
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/*****************************************************************************
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* Watchdog
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****************************************************************************/
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void __init orion5x_wdt_init(void)
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{
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orion_wdt_init();
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}
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/*****************************************************************************
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* Time handling
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****************************************************************************/
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void __init orion5x_init_early(void)
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{
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u32 rev, dev;
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const char *mbus_soc_name;
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orion_time_set_base(TIMER_VIRT_BASE);
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/*
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* Some Orion5x devices allocate their coherent buffers from atomic
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* context. Increase size of atomic coherent pool to make sure such
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* the allocations won't fail.
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*/
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init_dma_coherent_pool_size(SZ_1M);
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/* Initialize the MBUS driver */
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orion5x_pcie_id(&dev, &rev);
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if (dev == MV88F5281_DEV_ID)
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mbus_soc_name = "marvell,orion5x-88f5281-mbus";
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else if (dev == MV88F5182_DEV_ID)
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mbus_soc_name = "marvell,orion5x-88f5182-mbus";
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else if (dev == MV88F5181_DEV_ID)
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mbus_soc_name = "marvell,orion5x-88f5181-mbus";
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else if (dev == MV88F6183_DEV_ID)
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mbus_soc_name = "marvell,orion5x-88f6183-mbus";
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else
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mbus_soc_name = NULL;
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mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE,
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ORION5X_BRIDGE_WINS_SZ,
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ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ);
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}
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void orion5x_setup_wins(void)
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{
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/*
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* The PCIe windows will no longer be statically allocated
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* here once Orion5x is migrated to the pci-mvebu driver.
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*/
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mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_IO_PHYS_BASE,
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ORION5X_PCIE_IO_SIZE,
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ORION5X_PCIE_IO_BUS_BASE,
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MVEBU_MBUS_PCI_IO);
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mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_MEM_PHYS_BASE,
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ORION5X_PCIE_MEM_SIZE,
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MVEBU_MBUS_NO_REMAP,
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MVEBU_MBUS_PCI_MEM);
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mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_IO_PHYS_BASE,
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ORION5X_PCI_IO_SIZE,
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ORION5X_PCI_IO_BUS_BASE,
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MVEBU_MBUS_PCI_IO);
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mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_MEM_PHYS_BASE,
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ORION5X_PCI_MEM_SIZE,
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MVEBU_MBUS_NO_REMAP,
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MVEBU_MBUS_PCI_MEM);
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}
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int orion5x_tclk;
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int __init orion5x_find_tclk(void)
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{
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u32 dev, rev;
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orion5x_pcie_id(&dev, &rev);
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if (dev == MV88F6183_DEV_ID &&
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(readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
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return 133333333;
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return 166666667;
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}
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void __init orion5x_timer_init(void)
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{
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orion5x_tclk = orion5x_find_tclk();
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orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
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IRQ_ORION5X_BRIDGE, orion5x_tclk);
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}
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/*****************************************************************************
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* General
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****************************************************************************/
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/*
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* Identify device ID and rev from PCIe configuration header space '0'.
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*/
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void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
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{
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orion5x_pcie_id(dev, rev);
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if (*dev == MV88F5281_DEV_ID) {
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if (*rev == MV88F5281_REV_D2) {
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*dev_name = "MV88F5281-D2";
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} else if (*rev == MV88F5281_REV_D1) {
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*dev_name = "MV88F5281-D1";
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} else if (*rev == MV88F5281_REV_D0) {
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*dev_name = "MV88F5281-D0";
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} else {
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*dev_name = "MV88F5281-Rev-Unsupported";
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}
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} else if (*dev == MV88F5182_DEV_ID) {
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if (*rev == MV88F5182_REV_A2) {
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*dev_name = "MV88F5182-A2";
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} else {
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*dev_name = "MV88F5182-Rev-Unsupported";
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}
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} else if (*dev == MV88F5181_DEV_ID) {
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if (*rev == MV88F5181_REV_B1) {
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*dev_name = "MV88F5181-Rev-B1";
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} else if (*rev == MV88F5181L_REV_A1) {
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*dev_name = "MV88F5181L-Rev-A1";
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} else {
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*dev_name = "MV88F5181(L)-Rev-Unsupported";
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}
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} else if (*dev == MV88F6183_DEV_ID) {
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if (*rev == MV88F6183_REV_B0) {
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*dev_name = "MV88F6183-Rev-B0";
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} else {
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*dev_name = "MV88F6183-Rev-Unsupported";
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}
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} else {
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*dev_name = "Device-Unknown";
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}
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}
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void __init orion5x_init(void)
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{
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char *dev_name;
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u32 dev, rev;
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orion5x_id(&dev, &rev, &dev_name);
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printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
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/*
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* Setup Orion address map
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*/
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orion5x_setup_wins();
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/* Setup root of clk tree */
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clk_init();
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/*
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* Don't issue "Wait for Interrupt" instruction if we are
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* running on D0 5281 silicon.
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*/
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if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
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printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
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disable_hlt();
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}
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/*
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* The 5082/5181l/5182/6082/6082l/6183 have crypto
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* while 5180n/5181/5281 don't have crypto.
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*/
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if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
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dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
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orion5x_crypto_init();
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/*
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* Register watchdog driver
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*/
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orion5x_wdt_init();
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}
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void orion5x_restart(char mode, const char *cmd)
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{
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/*
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* Enable and issue soft reset
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*/
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orion5x_setbits(RSTOUTn_MASK, (1 << 2));
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orion5x_setbits(CPU_SOFT_RESET, 1);
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mdelay(200);
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orion5x_clrbits(CPU_SOFT_RESET, 1);
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}
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/*
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* Many orion-based systems have buggy bootloader implementations.
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* This is a common fixup for bogus memory tags.
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*/
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void __init tag_fixup_mem32(struct tag *t, char **from,
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struct meminfo *meminfo)
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{
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for (; t->hdr.size; t = tag_next(t))
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if (t->hdr.tag == ATAG_MEM &&
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(!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
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t->u.mem.start & ~PAGE_MASK)) {
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printk(KERN_WARNING
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"Clearing invalid memory bank %dKB@0x%08x\n",
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t->u.mem.size / 1024, t->u.mem.start);
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t->hdr.tag = 0;
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}
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}
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