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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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bf215cee23
Provides SHA512 x86_64 assembly routine optimized with SSSE3 instructions. Speedup of 40% or more has been measured over the generic implementation. Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
422 lines
13 KiB
ArmAsm
422 lines
13 KiB
ArmAsm
########################################################################
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# Implement fast SHA-512 with SSSE3 instructions. (x86_64)
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#
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# Copyright (C) 2013 Intel Corporation.
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#
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# Authors:
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# James Guilford <james.guilford@intel.com>
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# Kirk Yap <kirk.s.yap@intel.com>
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# David Cote <david.m.cote@intel.com>
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# Tim Chen <tim.c.chen@linux.intel.com>
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#
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# This software is available to you under a choice of one of two
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# licenses. You may choose to be licensed under the terms of the GNU
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# General Public License (GPL) Version 2, available from the file
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# COPYING in the main directory of this source tree, or the
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# OpenIB.org BSD license below:
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#
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# Redistribution and use in source and binary forms, with or
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# without modification, are permitted provided that the following
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# conditions are met:
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#
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# - Redistributions of source code must retain the above
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# copyright notice, this list of conditions and the following
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# disclaimer.
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#
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# - Redistributions in binary form must reproduce the above
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# copyright notice, this list of conditions and the following
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# disclaimer in the documentation and/or other materials
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# provided with the distribution.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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# SOFTWARE.
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#
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########################################################################
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#
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# This code is described in an Intel White-Paper:
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# "Fast SHA-512 Implementations on Intel Architecture Processors"
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#
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# To find it, surf to http://www.intel.com/p/en_US/embedded
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# and search for that title.
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#
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########################################################################
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#include <linux/linkage.h>
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.text
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# Virtual Registers
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# ARG1
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msg = %rdi
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# ARG2
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digest = %rsi
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# ARG3
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msglen = %rdx
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T1 = %rcx
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T2 = %r8
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a_64 = %r9
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b_64 = %r10
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c_64 = %r11
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d_64 = %r12
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e_64 = %r13
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f_64 = %r14
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g_64 = %r15
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h_64 = %rbx
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tmp0 = %rax
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# Local variables (stack frame)
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W_SIZE = 80*8
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WK_SIZE = 2*8
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RSPSAVE_SIZE = 1*8
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GPRSAVE_SIZE = 5*8
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frame_W = 0
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frame_WK = frame_W + W_SIZE
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frame_RSPSAVE = frame_WK + WK_SIZE
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frame_GPRSAVE = frame_RSPSAVE + RSPSAVE_SIZE
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frame_size = frame_GPRSAVE + GPRSAVE_SIZE
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# Useful QWORD "arrays" for simpler memory references
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# MSG, DIGEST, K_t, W_t are arrays
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# WK_2(t) points to 1 of 2 qwords at frame.WK depdending on t being odd/even
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# Input message (arg1)
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#define MSG(i) 8*i(msg)
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# Output Digest (arg2)
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#define DIGEST(i) 8*i(digest)
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# SHA Constants (static mem)
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#define K_t(i) 8*i+K512(%rip)
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# Message Schedule (stack frame)
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#define W_t(i) 8*i+frame_W(%rsp)
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# W[t]+K[t] (stack frame)
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#define WK_2(i) 8*((i%2))+frame_WK(%rsp)
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.macro RotateState
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# Rotate symbols a..h right
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TMP = h_64
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h_64 = g_64
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g_64 = f_64
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f_64 = e_64
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e_64 = d_64
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d_64 = c_64
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c_64 = b_64
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b_64 = a_64
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a_64 = TMP
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.endm
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.macro SHA512_Round rnd
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# Compute Round %%t
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mov f_64, T1 # T1 = f
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mov e_64, tmp0 # tmp = e
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xor g_64, T1 # T1 = f ^ g
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ror $23, tmp0 # 41 # tmp = e ror 23
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and e_64, T1 # T1 = (f ^ g) & e
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xor e_64, tmp0 # tmp = (e ror 23) ^ e
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xor g_64, T1 # T1 = ((f ^ g) & e) ^ g = CH(e,f,g)
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idx = \rnd
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add WK_2(idx), T1 # W[t] + K[t] from message scheduler
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ror $4, tmp0 # 18 # tmp = ((e ror 23) ^ e) ror 4
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xor e_64, tmp0 # tmp = (((e ror 23) ^ e) ror 4) ^ e
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mov a_64, T2 # T2 = a
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add h_64, T1 # T1 = CH(e,f,g) + W[t] + K[t] + h
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ror $14, tmp0 # 14 # tmp = ((((e ror23)^e)ror4)^e)ror14 = S1(e)
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add tmp0, T1 # T1 = CH(e,f,g) + W[t] + K[t] + S1(e)
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mov a_64, tmp0 # tmp = a
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xor c_64, T2 # T2 = a ^ c
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and c_64, tmp0 # tmp = a & c
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and b_64, T2 # T2 = (a ^ c) & b
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xor tmp0, T2 # T2 = ((a ^ c) & b) ^ (a & c) = Maj(a,b,c)
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mov a_64, tmp0 # tmp = a
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ror $5, tmp0 # 39 # tmp = a ror 5
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xor a_64, tmp0 # tmp = (a ror 5) ^ a
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add T1, d_64 # e(next_state) = d + T1
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ror $6, tmp0 # 34 # tmp = ((a ror 5) ^ a) ror 6
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xor a_64, tmp0 # tmp = (((a ror 5) ^ a) ror 6) ^ a
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lea (T1, T2), h_64 # a(next_state) = T1 + Maj(a,b,c)
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ror $28, tmp0 # 28 # tmp = ((((a ror5)^a)ror6)^a)ror28 = S0(a)
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add tmp0, h_64 # a(next_state) = T1 + Maj(a,b,c) S0(a)
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RotateState
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.endm
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.macro SHA512_2Sched_2Round_sse rnd
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# Compute rounds t-2 and t-1
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# Compute message schedule QWORDS t and t+1
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# Two rounds are computed based on the values for K[t-2]+W[t-2] and
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# K[t-1]+W[t-1] which were previously stored at WK_2 by the message
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# scheduler.
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# The two new schedule QWORDS are stored at [W_t(%%t)] and [W_t(%%t+1)].
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# They are then added to their respective SHA512 constants at
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# [K_t(%%t)] and [K_t(%%t+1)] and stored at dqword [WK_2(%%t)]
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# For brievity, the comments following vectored instructions only refer to
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# the first of a pair of QWORDS.
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# Eg. XMM2=W[t-2] really means XMM2={W[t-2]|W[t-1]}
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# The computation of the message schedule and the rounds are tightly
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# stitched to take advantage of instruction-level parallelism.
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# For clarity, integer instructions (for the rounds calculation) are indented
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# by one tab. Vectored instructions (for the message scheduler) are indented
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# by two tabs.
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mov f_64, T1
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idx = \rnd -2
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movdqa W_t(idx), %xmm2 # XMM2 = W[t-2]
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xor g_64, T1
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and e_64, T1
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movdqa %xmm2, %xmm0 # XMM0 = W[t-2]
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xor g_64, T1
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idx = \rnd
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add WK_2(idx), T1
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idx = \rnd - 15
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movdqu W_t(idx), %xmm5 # XMM5 = W[t-15]
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mov e_64, tmp0
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ror $23, tmp0 # 41
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movdqa %xmm5, %xmm3 # XMM3 = W[t-15]
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xor e_64, tmp0
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ror $4, tmp0 # 18
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psrlq $61-19, %xmm0 # XMM0 = W[t-2] >> 42
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xor e_64, tmp0
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ror $14, tmp0 # 14
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psrlq $(8-7), %xmm3 # XMM3 = W[t-15] >> 1
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add tmp0, T1
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add h_64, T1
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pxor %xmm2, %xmm0 # XMM0 = (W[t-2] >> 42) ^ W[t-2]
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mov a_64, T2
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xor c_64, T2
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pxor %xmm5, %xmm3 # XMM3 = (W[t-15] >> 1) ^ W[t-15]
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and b_64, T2
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mov a_64, tmp0
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psrlq $(19-6), %xmm0 # XMM0 = ((W[t-2]>>42)^W[t-2])>>13
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and c_64, tmp0
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xor tmp0, T2
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psrlq $(7-1), %xmm3 # XMM3 = ((W[t-15]>>1)^W[t-15])>>6
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mov a_64, tmp0
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ror $5, tmp0 # 39
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pxor %xmm2, %xmm0 # XMM0 = (((W[t-2]>>42)^W[t-2])>>13)^W[t-2]
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xor a_64, tmp0
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ror $6, tmp0 # 34
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pxor %xmm5, %xmm3 # XMM3 = (((W[t-15]>>1)^W[t-15])>>6)^W[t-15]
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xor a_64, tmp0
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ror $28, tmp0 # 28
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psrlq $6, %xmm0 # XMM0 = ((((W[t-2]>>42)^W[t-2])>>13)^W[t-2])>>6
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add tmp0, T2
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add T1, d_64
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psrlq $1, %xmm3 # XMM3 = (((W[t-15]>>1)^W[t-15])>>6)^W[t-15]>>1
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lea (T1, T2), h_64
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RotateState
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movdqa %xmm2, %xmm1 # XMM1 = W[t-2]
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mov f_64, T1
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xor g_64, T1
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movdqa %xmm5, %xmm4 # XMM4 = W[t-15]
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and e_64, T1
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xor g_64, T1
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psllq $(64-19)-(64-61) , %xmm1 # XMM1 = W[t-2] << 42
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idx = \rnd + 1
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add WK_2(idx), T1
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mov e_64, tmp0
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psllq $(64-1)-(64-8), %xmm4 # XMM4 = W[t-15] << 7
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ror $23, tmp0 # 41
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xor e_64, tmp0
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pxor %xmm2, %xmm1 # XMM1 = (W[t-2] << 42)^W[t-2]
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ror $4, tmp0 # 18
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xor e_64, tmp0
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pxor %xmm5, %xmm4 # XMM4 = (W[t-15]<<7)^W[t-15]
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ror $14, tmp0 # 14
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add tmp0, T1
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psllq $(64-61), %xmm1 # XMM1 = ((W[t-2] << 42)^W[t-2])<<3
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add h_64, T1
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mov a_64, T2
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psllq $(64-8), %xmm4 # XMM4 = ((W[t-15]<<7)^W[t-15])<<56
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xor c_64, T2
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and b_64, T2
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pxor %xmm1, %xmm0 # XMM0 = s1(W[t-2])
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mov a_64, tmp0
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and c_64, tmp0
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idx = \rnd - 7
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movdqu W_t(idx), %xmm1 # XMM1 = W[t-7]
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xor tmp0, T2
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pxor %xmm4, %xmm3 # XMM3 = s0(W[t-15])
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mov a_64, tmp0
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paddq %xmm3, %xmm0 # XMM0 = s1(W[t-2]) + s0(W[t-15])
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ror $5, tmp0 # 39
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idx =\rnd-16
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paddq W_t(idx), %xmm0 # XMM0 = s1(W[t-2]) + s0(W[t-15]) + W[t-16]
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xor a_64, tmp0
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paddq %xmm1, %xmm0 # XMM0 = s1(W[t-2]) + W[t-7] + s0(W[t-15]) + W[t-16]
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ror $6, tmp0 # 34
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movdqa %xmm0, W_t(\rnd) # Store scheduled qwords
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xor a_64, tmp0
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paddq K_t(\rnd), %xmm0 # Compute W[t]+K[t]
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ror $28, tmp0 # 28
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idx = \rnd
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movdqa %xmm0, WK_2(idx) # Store W[t]+K[t] for next rounds
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add tmp0, T2
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add T1, d_64
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lea (T1, T2), h_64
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RotateState
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.endm
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########################################################################
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# void sha512_transform_ssse3(const void* M, void* D, u64 L)#
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# Purpose: Updates the SHA512 digest stored at D with the message stored in M.
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# The size of the message pointed to by M must be an integer multiple of SHA512
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# message blocks.
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# L is the message length in SHA512 blocks.
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########################################################################
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ENTRY(sha512_transform_ssse3)
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cmp $0, msglen
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je nowork
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# Allocate Stack Space
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mov %rsp, %rax
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sub $frame_size, %rsp
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and $~(0x20 - 1), %rsp
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mov %rax, frame_RSPSAVE(%rsp)
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# Save GPRs
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mov %rbx, frame_GPRSAVE(%rsp)
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mov %r12, frame_GPRSAVE +8*1(%rsp)
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mov %r13, frame_GPRSAVE +8*2(%rsp)
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mov %r14, frame_GPRSAVE +8*3(%rsp)
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mov %r15, frame_GPRSAVE +8*4(%rsp)
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updateblock:
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# Load state variables
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mov DIGEST(0), a_64
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mov DIGEST(1), b_64
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mov DIGEST(2), c_64
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mov DIGEST(3), d_64
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mov DIGEST(4), e_64
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mov DIGEST(5), f_64
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mov DIGEST(6), g_64
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mov DIGEST(7), h_64
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t = 0
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.rept 80/2 + 1
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# (80 rounds) / (2 rounds/iteration) + (1 iteration)
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# +1 iteration because the scheduler leads hashing by 1 iteration
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.if t < 2
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# BSWAP 2 QWORDS
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movdqa XMM_QWORD_BSWAP(%rip), %xmm1
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movdqu MSG(t), %xmm0
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pshufb %xmm1, %xmm0 # BSWAP
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movdqa %xmm0, W_t(t) # Store Scheduled Pair
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paddq K_t(t), %xmm0 # Compute W[t]+K[t]
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movdqa %xmm0, WK_2(t) # Store into WK for rounds
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.elseif t < 16
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# BSWAP 2 QWORDS# Compute 2 Rounds
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movdqu MSG(t), %xmm0
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pshufb %xmm1, %xmm0 # BSWAP
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SHA512_Round t-2 # Round t-2
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movdqa %xmm0, W_t(t) # Store Scheduled Pair
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paddq K_t(t), %xmm0 # Compute W[t]+K[t]
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SHA512_Round t-1 # Round t-1
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movdqa %xmm0, WK_2(t) # Store W[t]+K[t] into WK
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.elseif t < 79
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# Schedule 2 QWORDS# Compute 2 Rounds
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SHA512_2Sched_2Round_sse t
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.else
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# Compute 2 Rounds
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SHA512_Round t-2
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SHA512_Round t-1
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.endif
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t = t+2
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.endr
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# Update digest
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add a_64, DIGEST(0)
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add b_64, DIGEST(1)
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add c_64, DIGEST(2)
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add d_64, DIGEST(3)
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add e_64, DIGEST(4)
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add f_64, DIGEST(5)
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add g_64, DIGEST(6)
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add h_64, DIGEST(7)
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# Advance to next message block
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add $16*8, msg
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dec msglen
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jnz updateblock
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# Restore GPRs
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mov frame_GPRSAVE(%rsp), %rbx
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mov frame_GPRSAVE +8*1(%rsp), %r12
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mov frame_GPRSAVE +8*2(%rsp), %r13
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mov frame_GPRSAVE +8*3(%rsp), %r14
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mov frame_GPRSAVE +8*4(%rsp), %r15
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# Restore Stack Pointer
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mov frame_RSPSAVE(%rsp), %rsp
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nowork:
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ret
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ENDPROC(sha512_transform_ssse3)
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########################################################################
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### Binary Data
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.data
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.align 16
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# Mask for byte-swapping a couple of qwords in an XMM register using (v)pshufb.
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XMM_QWORD_BSWAP:
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.octa 0x08090a0b0c0d0e0f0001020304050607
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# K[t] used in SHA512 hashing
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K512:
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.quad 0x428a2f98d728ae22,0x7137449123ef65cd
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.quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc
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.quad 0x3956c25bf348b538,0x59f111f1b605d019
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.quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118
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.quad 0xd807aa98a3030242,0x12835b0145706fbe
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.quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2
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.quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1
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.quad 0x9bdc06a725c71235,0xc19bf174cf692694
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.quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3
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.quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65
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.quad 0x2de92c6f592b0275,0x4a7484aa6ea6e483
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.quad 0x5cb0a9dcbd41fbd4,0x76f988da831153b5
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.quad 0x983e5152ee66dfab,0xa831c66d2db43210
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.quad 0xb00327c898fb213f,0xbf597fc7beef0ee4
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.quad 0xc6e00bf33da88fc2,0xd5a79147930aa725
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.quad 0x06ca6351e003826f,0x142929670a0e6e70
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.quad 0x27b70a8546d22ffc,0x2e1b21385c26c926
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.quad 0x4d2c6dfc5ac42aed,0x53380d139d95b3df
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.quad 0x650a73548baf63de,0x766a0abb3c77b2a8
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.quad 0x81c2c92e47edaee6,0x92722c851482353b
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.quad 0xa2bfe8a14cf10364,0xa81a664bbc423001
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.quad 0xc24b8b70d0f89791,0xc76c51a30654be30
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.quad 0xd192e819d6ef5218,0xd69906245565a910
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.quad 0xf40e35855771202a,0x106aa07032bbd1b8
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.quad 0x19a4c116b8d2d0c8,0x1e376c085141ab53
|
|
.quad 0x2748774cdf8eeb99,0x34b0bcb5e19b48a8
|
|
.quad 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb
|
|
.quad 0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3
|
|
.quad 0x748f82ee5defb2fc,0x78a5636f43172f60
|
|
.quad 0x84c87814a1f0ab72,0x8cc702081a6439ec
|
|
.quad 0x90befffa23631e28,0xa4506cebde82bde9
|
|
.quad 0xbef9a3f7b2c67915,0xc67178f2e372532b
|
|
.quad 0xca273eceea26619c,0xd186b8c721c0c207
|
|
.quad 0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178
|
|
.quad 0x06f067aa72176fba,0x0a637dc5a2c898a6
|
|
.quad 0x113f9804bef90dae,0x1b710b35131c471b
|
|
.quad 0x28db77f523047d84,0x32caab7b40c72493
|
|
.quad 0x3c9ebe0a15c9bebc,0x431d67c49c100d4c
|
|
.quad 0x4cc5d4becb3e42b6,0x597f299cfc657e2a
|
|
.quad 0x5fcb6fab3ad6faec,0x6c44198c4a475817
|