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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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f5c3ef21db
Check for the presence of the '/cpus' OF node before dereferencing it blindly: [ 4.181793] Unable to handle kernel NULL pointer dereference at virtual address 0000001c [ 4.181793] pgd = c0004000 [ 4.181823] [0000001c] *pgd=00000000 [ 4.181823] Internal error: Oops: 5 [#1] SMP ARM [ 4.181823] Modules linked in: [ 4.181823] CPU: 1 Tainted: G W (3.8.0-15-generic #25~hbankD) [ 4.181854] PC is at of_get_next_child+0x64/0x70 [ 4.181854] LR is at of_get_next_child+0x24/0x70 [ 4.181854] pc : [<c04fda18>] lr : [<c04fd9d8>] psr: 60000113 [ 4.181854] sp : ed891ec0 ip : ed891ec0 fp : ed891ed4 [ 4.181884] r10: c04dafd0 r9 : c098690c r8 : c0936208 [ 4.181884] r7 : ed890000 r6 : c0a63d00 r5 : 00000000 r4 : 00000000 [ 4.181884] r3 : 00000000 r2 : 00000000 r1 : 00000000 r0 : c0b2acc8 [ 4.181884] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel [ 4.181884] Control: 10c5387d Table: adcb804a DAC: 00000015 [ 4.181915] Process swapper/0 (pid: 1, stack limit = 0xed890238) [ 4.181915] Stack: (0xed891ec0 to 0xed892000) [ 4.181915] 1ec0: c09b7b70 00000007 ed891efc ed891ed8 c04daff4 c04fd9c0 00000000 c09b7b70 [ 4.181915] 1ee0: 00000007 c0a63d00 ed890000 c0936208 ed891f54 ed891f00 c00088e0 c04dafdc [ 4.181945] 1f00: ed891f54 ed891f10 c006e940 00000000 00000000 00000007 00000007 c08a4914 [ 4.181945] 1f20: 00000000 c07dbd30 c0a63d00 c09b7b70 00000007 c0a63d00 000000bc c0936208 [ 4.181945] 1f40: c098690c c0986914 ed891f94 ed891f58 c0936a40 c00087bc 00000007 00000007 [ 4.181976] 1f60: c0936208 be8bda20 b6eea010 c0a63d00 c064547c 00000000 00000000 00000000 [ 4.181976] 1f80: 00000000 00000000 ed891fac ed891f98 c0645498 c09368c8 00000000 00000000 [ 4.181976] 1fa0: 00000000 ed891fb0 c0014658 c0645488 00000000 00000000 00000000 00000000 [ 4.182006] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 4.182006] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000 [ 4.182037] [<c04fda18>] (of_get_next_child+0x64/0x70) from [<c04daff4>] (cpu0_cpufreq_driver_init+0x24/0x284) [ 4.182067] [<c04daff4>] (cpu0_cpufreq_driver_init+0x24/0x284) from [<c00088e0>] (do_one_initcall+0x130/0x1b0) [ 4.182067] [<c00088e0>] (do_one_initcall+0x130/0x1b0) from [<c0936a40>] (kernel_init_freeable+0x184/0x24c) [ 4.182098] [<c0936a40>] (kernel_init_freeable+0x184/0x24c) from [<c0645498>] (kernel_init+0x1c/0xf4) [ 4.182128] [<c0645498>] (kernel_init+0x1c/0xf4) from [<c0014658>] (ret_from_fork+0x14/0x20) [ 4.182128] Code: f57ff04f e320f004 e89da830 e89da830 (e595001c) [ 4.182128] ---[ end trace 634903a22e8609cb ]--- [ 4.182189] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b [ 4.182189] [ 4.642395] CPU0: stopping [rjw: Changelog] Signed-off-by: Paolo Pisati <paolo.pisati@canonical.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
295 lines
7.0 KiB
C
295 lines
7.0 KiB
C
/*
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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*
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* The OPP code in function cpu0_set_target() is reused from
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* drivers/cpufreq/omap-cpufreq.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/opp.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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static unsigned int transition_latency;
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static unsigned int voltage_tolerance; /* in percentage */
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static struct device *cpu_dev;
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static struct clk *cpu_clk;
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static struct regulator *cpu_reg;
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static struct cpufreq_frequency_table *freq_table;
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static int cpu0_verify_speed(struct cpufreq_policy *policy)
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{
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return cpufreq_frequency_table_verify(policy, freq_table);
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}
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static unsigned int cpu0_get_speed(unsigned int cpu)
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{
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return clk_get_rate(cpu_clk) / 1000;
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}
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static int cpu0_set_target(struct cpufreq_policy *policy,
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unsigned int target_freq, unsigned int relation)
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{
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struct cpufreq_freqs freqs;
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struct opp *opp;
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unsigned long freq_Hz, volt = 0, volt_old = 0, tol = 0;
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unsigned int index, cpu;
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int ret;
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ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
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relation, &index);
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if (ret) {
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pr_err("failed to match target freqency %d: %d\n",
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target_freq, ret);
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return ret;
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}
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freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
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if (freq_Hz < 0)
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freq_Hz = freq_table[index].frequency * 1000;
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freqs.new = freq_Hz / 1000;
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freqs.old = clk_get_rate(cpu_clk) / 1000;
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if (freqs.old == freqs.new)
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return 0;
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for_each_online_cpu(cpu) {
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freqs.cpu = cpu;
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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}
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if (cpu_reg) {
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rcu_read_lock();
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opp = opp_find_freq_ceil(cpu_dev, &freq_Hz);
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if (IS_ERR(opp)) {
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rcu_read_unlock();
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pr_err("failed to find OPP for %ld\n", freq_Hz);
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return PTR_ERR(opp);
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}
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volt = opp_get_voltage(opp);
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rcu_read_unlock();
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tol = volt * voltage_tolerance / 100;
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volt_old = regulator_get_voltage(cpu_reg);
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}
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pr_debug("%u MHz, %ld mV --> %u MHz, %ld mV\n",
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freqs.old / 1000, volt_old ? volt_old / 1000 : -1,
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freqs.new / 1000, volt ? volt / 1000 : -1);
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/* scaling up? scale voltage before frequency */
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if (cpu_reg && freqs.new > freqs.old) {
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ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
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if (ret) {
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pr_err("failed to scale voltage up: %d\n", ret);
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freqs.new = freqs.old;
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return ret;
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}
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}
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ret = clk_set_rate(cpu_clk, freqs.new * 1000);
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if (ret) {
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pr_err("failed to set clock rate: %d\n", ret);
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if (cpu_reg)
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regulator_set_voltage_tol(cpu_reg, volt_old, tol);
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return ret;
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}
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/* scaling down? scale voltage after frequency */
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if (cpu_reg && freqs.new < freqs.old) {
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ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
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if (ret) {
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pr_err("failed to scale voltage down: %d\n", ret);
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clk_set_rate(cpu_clk, freqs.old * 1000);
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freqs.new = freqs.old;
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return ret;
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}
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}
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for_each_online_cpu(cpu) {
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freqs.cpu = cpu;
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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}
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return 0;
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}
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static int cpu0_cpufreq_init(struct cpufreq_policy *policy)
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{
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int ret;
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if (policy->cpu != 0)
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return -EINVAL;
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ret = cpufreq_frequency_table_cpuinfo(policy, freq_table);
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if (ret) {
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pr_err("invalid frequency table: %d\n", ret);
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return ret;
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}
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policy->cpuinfo.transition_latency = transition_latency;
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policy->cur = clk_get_rate(cpu_clk) / 1000;
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/*
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* The driver only supports the SMP configuartion where all processors
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* share the clock and voltage and clock. Use cpufreq affected_cpus
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* interface to have all CPUs scaled together.
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*/
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cpumask_setall(policy->cpus);
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cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
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return 0;
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}
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static int cpu0_cpufreq_exit(struct cpufreq_policy *policy)
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{
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cpufreq_frequency_table_put_attr(policy->cpu);
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return 0;
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}
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static struct freq_attr *cpu0_cpufreq_attr[] = {
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&cpufreq_freq_attr_scaling_available_freqs,
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NULL,
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};
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static struct cpufreq_driver cpu0_cpufreq_driver = {
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.flags = CPUFREQ_STICKY,
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.verify = cpu0_verify_speed,
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.target = cpu0_set_target,
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.get = cpu0_get_speed,
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.init = cpu0_cpufreq_init,
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.exit = cpu0_cpufreq_exit,
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.name = "generic_cpu0",
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.attr = cpu0_cpufreq_attr,
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};
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static int cpu0_cpufreq_probe(struct platform_device *pdev)
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{
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struct device_node *np, *parent;
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int ret;
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parent = of_find_node_by_path("/cpus");
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if (!parent) {
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pr_err("failed to find OF /cpus\n");
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return -ENOENT;
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}
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for_each_child_of_node(parent, np) {
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if (of_get_property(np, "operating-points", NULL))
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break;
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}
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if (!np) {
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pr_err("failed to find cpu0 node\n");
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return -ENOENT;
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}
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cpu_dev = &pdev->dev;
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cpu_dev->of_node = np;
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cpu_clk = devm_clk_get(cpu_dev, NULL);
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if (IS_ERR(cpu_clk)) {
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ret = PTR_ERR(cpu_clk);
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pr_err("failed to get cpu0 clock: %d\n", ret);
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goto out_put_node;
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}
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cpu_reg = devm_regulator_get(cpu_dev, "cpu0");
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if (IS_ERR(cpu_reg)) {
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pr_warn("failed to get cpu0 regulator\n");
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cpu_reg = NULL;
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}
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ret = of_init_opp_table(cpu_dev);
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if (ret) {
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pr_err("failed to init OPP table: %d\n", ret);
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goto out_put_node;
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}
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ret = opp_init_cpufreq_table(cpu_dev, &freq_table);
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if (ret) {
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pr_err("failed to init cpufreq table: %d\n", ret);
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goto out_put_node;
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}
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of_property_read_u32(np, "voltage-tolerance", &voltage_tolerance);
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if (of_property_read_u32(np, "clock-latency", &transition_latency))
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transition_latency = CPUFREQ_ETERNAL;
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if (cpu_reg) {
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struct opp *opp;
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unsigned long min_uV, max_uV;
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int i;
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/*
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* OPP is maintained in order of increasing frequency, and
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* freq_table initialised from OPP is therefore sorted in the
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* same order.
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*/
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for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
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;
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rcu_read_lock();
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opp = opp_find_freq_exact(cpu_dev,
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freq_table[0].frequency * 1000, true);
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min_uV = opp_get_voltage(opp);
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opp = opp_find_freq_exact(cpu_dev,
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freq_table[i-1].frequency * 1000, true);
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max_uV = opp_get_voltage(opp);
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rcu_read_unlock();
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ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
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if (ret > 0)
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transition_latency += ret * 1000;
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}
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ret = cpufreq_register_driver(&cpu0_cpufreq_driver);
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if (ret) {
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pr_err("failed register driver: %d\n", ret);
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goto out_free_table;
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}
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of_node_put(np);
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return 0;
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out_free_table:
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opp_free_cpufreq_table(cpu_dev, &freq_table);
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out_put_node:
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of_node_put(np);
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return ret;
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}
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static int cpu0_cpufreq_remove(struct platform_device *pdev)
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{
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cpufreq_unregister_driver(&cpu0_cpufreq_driver);
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opp_free_cpufreq_table(cpu_dev, &freq_table);
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return 0;
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}
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static struct platform_driver cpu0_cpufreq_platdrv = {
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.driver = {
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.name = "cpufreq-cpu0",
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.owner = THIS_MODULE,
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},
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.probe = cpu0_cpufreq_probe,
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.remove = cpu0_cpufreq_remove,
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};
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module_platform_driver(cpu0_cpufreq_platdrv);
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MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
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MODULE_DESCRIPTION("Generic CPU0 cpufreq driver");
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MODULE_LICENSE("GPL");
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