mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 21:28:03 +07:00
508 lines
16 KiB
C
508 lines
16 KiB
C
#ifndef ADRENO_COMMON_XML
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#define ADRENO_COMMON_XML
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/* Autogenerated file, DO NOT EDIT manually!
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This file was generated by the rules-ng-ng headergen tool in this git repository:
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http://github.com/freedreno/envytools/
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git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
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Copyright (C) 2013-2017 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial
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portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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enum adreno_pa_su_sc_draw {
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PC_DRAW_POINTS = 0,
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PC_DRAW_LINES = 1,
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PC_DRAW_TRIANGLES = 2,
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};
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enum adreno_compare_func {
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FUNC_NEVER = 0,
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FUNC_LESS = 1,
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FUNC_EQUAL = 2,
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FUNC_LEQUAL = 3,
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FUNC_GREATER = 4,
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FUNC_NOTEQUAL = 5,
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FUNC_GEQUAL = 6,
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FUNC_ALWAYS = 7,
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};
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enum adreno_stencil_op {
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STENCIL_KEEP = 0,
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STENCIL_ZERO = 1,
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STENCIL_REPLACE = 2,
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STENCIL_INCR_CLAMP = 3,
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STENCIL_DECR_CLAMP = 4,
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STENCIL_INVERT = 5,
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STENCIL_INCR_WRAP = 6,
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STENCIL_DECR_WRAP = 7,
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};
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enum adreno_rb_blend_factor {
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FACTOR_ZERO = 0,
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FACTOR_ONE = 1,
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FACTOR_SRC_COLOR = 4,
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FACTOR_ONE_MINUS_SRC_COLOR = 5,
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FACTOR_SRC_ALPHA = 6,
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FACTOR_ONE_MINUS_SRC_ALPHA = 7,
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FACTOR_DST_COLOR = 8,
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FACTOR_ONE_MINUS_DST_COLOR = 9,
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FACTOR_DST_ALPHA = 10,
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FACTOR_ONE_MINUS_DST_ALPHA = 11,
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FACTOR_CONSTANT_COLOR = 12,
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FACTOR_ONE_MINUS_CONSTANT_COLOR = 13,
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FACTOR_CONSTANT_ALPHA = 14,
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FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15,
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FACTOR_SRC_ALPHA_SATURATE = 16,
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FACTOR_SRC1_COLOR = 20,
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FACTOR_ONE_MINUS_SRC1_COLOR = 21,
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FACTOR_SRC1_ALPHA = 22,
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FACTOR_ONE_MINUS_SRC1_ALPHA = 23,
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};
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enum adreno_rb_surface_endian {
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ENDIAN_NONE = 0,
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ENDIAN_8IN16 = 1,
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ENDIAN_8IN32 = 2,
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ENDIAN_16IN32 = 3,
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ENDIAN_8IN64 = 4,
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ENDIAN_8IN128 = 5,
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};
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enum adreno_rb_dither_mode {
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DITHER_DISABLE = 0,
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DITHER_ALWAYS = 1,
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DITHER_IF_ALPHA_OFF = 2,
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};
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enum adreno_rb_depth_format {
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DEPTHX_16 = 0,
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DEPTHX_24_8 = 1,
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DEPTHX_32 = 2,
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};
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enum adreno_rb_copy_control_mode {
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RB_COPY_RESOLVE = 1,
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RB_COPY_CLEAR = 2,
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RB_COPY_DEPTH_STENCIL = 5,
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};
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enum a3xx_rop_code {
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ROP_CLEAR = 0,
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ROP_NOR = 1,
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ROP_AND_INVERTED = 2,
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ROP_COPY_INVERTED = 3,
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ROP_AND_REVERSE = 4,
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ROP_INVERT = 5,
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ROP_NAND = 7,
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ROP_AND = 8,
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ROP_EQUIV = 9,
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ROP_NOOP = 10,
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ROP_OR_INVERTED = 11,
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ROP_OR_REVERSE = 13,
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ROP_OR = 14,
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ROP_SET = 15,
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};
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enum a3xx_render_mode {
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RB_RENDERING_PASS = 0,
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RB_TILING_PASS = 1,
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RB_RESOLVE_PASS = 2,
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RB_COMPUTE_PASS = 3,
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};
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enum a3xx_msaa_samples {
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MSAA_ONE = 0,
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MSAA_TWO = 1,
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MSAA_FOUR = 2,
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};
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enum a3xx_threadmode {
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MULTI = 0,
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SINGLE = 1,
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};
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enum a3xx_instrbuffermode {
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CACHE = 0,
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BUFFER = 1,
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};
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enum a3xx_threadsize {
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TWO_QUADS = 0,
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FOUR_QUADS = 1,
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};
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enum a3xx_color_swap {
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WZYX = 0,
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WXYZ = 1,
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ZYXW = 2,
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XYZW = 3,
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};
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enum a3xx_rb_blend_opcode {
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BLEND_DST_PLUS_SRC = 0,
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BLEND_SRC_MINUS_DST = 1,
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BLEND_DST_MINUS_SRC = 2,
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BLEND_MIN_DST_SRC = 3,
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BLEND_MAX_DST_SRC = 4,
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};
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#define REG_AXXX_CP_RB_BASE 0x000001c0
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#define REG_AXXX_CP_RB_CNTL 0x000001c1
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#define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f
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#define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0
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static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val)
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{
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return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK;
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}
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#define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00
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#define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8
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static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val)
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{
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return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK;
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}
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#define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000
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#define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16
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static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val)
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{
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return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK;
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}
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#define AXXX_CP_RB_CNTL_POLL_EN 0x00100000
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#define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000
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#define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000
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#define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3
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#define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003
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#define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0
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static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val)
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{
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return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK;
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}
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#define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc
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#define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2
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static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val)
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{
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return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK;
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}
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#define REG_AXXX_CP_RB_RPTR 0x000001c4
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#define REG_AXXX_CP_RB_WPTR 0x000001c5
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#define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6
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#define REG_AXXX_CP_RB_RPTR_WR 0x000001c7
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#define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8
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#define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5
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#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f
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#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0
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static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val)
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{
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return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK;
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}
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#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00
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#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8
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static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val)
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{
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return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK;
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}
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#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000
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#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16
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static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val)
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{
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return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK;
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}
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#define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6
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#define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000
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#define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16
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static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val)
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{
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return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK;
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}
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#define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000
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#define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24
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static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val)
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{
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return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK;
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}
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#define REG_AXXX_CP_CSQ_AVAIL 0x000001d7
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#define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f
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#define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0
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static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val)
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{
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return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK;
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}
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#define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00
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#define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8
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static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val)
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{
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return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK;
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}
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#define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000
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#define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16
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static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val)
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{
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return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK;
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}
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#define REG_AXXX_CP_STQ_AVAIL 0x000001d8
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#define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f
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#define AXXX_CP_STQ_AVAIL_ST__SHIFT 0
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static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val)
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{
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return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK;
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}
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#define REG_AXXX_CP_MEQ_AVAIL 0x000001d9
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#define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f
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#define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0
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static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val)
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{
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return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK;
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}
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#define REG_AXXX_SCRATCH_UMSK 0x000001dc
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#define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff
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#define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0
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static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val)
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{
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return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK;
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}
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#define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000
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#define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16
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static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val)
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{
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return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK;
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}
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#define REG_AXXX_SCRATCH_ADDR 0x000001dd
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#define REG_AXXX_CP_ME_RDADDR 0x000001ea
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#define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec
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#define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed
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#define REG_AXXX_CP_INT_CNTL 0x000001f2
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#define REG_AXXX_CP_INT_STATUS 0x000001f3
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#define REG_AXXX_CP_INT_ACK 0x000001f4
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#define REG_AXXX_CP_ME_CNTL 0x000001f6
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#define AXXX_CP_ME_CNTL_BUSY 0x20000000
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#define AXXX_CP_ME_CNTL_HALT 0x10000000
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#define REG_AXXX_CP_ME_STATUS 0x000001f7
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#define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8
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#define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9
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#define REG_AXXX_CP_ME_RAM_DATA 0x000001fa
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#define REG_AXXX_CP_DEBUG 0x000001fc
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#define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000
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#define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000
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#define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000
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#define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000
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#define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000
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#define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000
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#define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000
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#define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000
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#define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd
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#define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f
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#define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0
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static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val)
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{
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return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK;
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}
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#define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000
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#define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16
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static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val)
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{
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return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK;
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}
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#define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe
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#define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f
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#define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0
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static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val)
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{
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return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK;
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}
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#define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000
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#define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16
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static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val)
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{
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return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK;
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}
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#define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff
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#define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f
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#define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0
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static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val)
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{
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return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK;
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}
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#define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000
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#define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16
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static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
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{
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return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK;
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}
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#define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440
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#define REG_AXXX_CP_STQ_ST_STAT 0x00000443
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#define REG_AXXX_CP_ST_BASE 0x0000044d
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#define REG_AXXX_CP_ST_BUFSZ 0x0000044e
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#define REG_AXXX_CP_MEQ_STAT 0x0000044f
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#define REG_AXXX_CP_MIU_TAG_STAT 0x00000452
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#define REG_AXXX_CP_BIN_MASK_LO 0x00000454
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#define REG_AXXX_CP_BIN_MASK_HI 0x00000455
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#define REG_AXXX_CP_BIN_SELECT_LO 0x00000456
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#define REG_AXXX_CP_BIN_SELECT_HI 0x00000457
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#define REG_AXXX_CP_IB1_BASE 0x00000458
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#define REG_AXXX_CP_IB1_BUFSZ 0x00000459
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#define REG_AXXX_CP_IB2_BASE 0x0000045a
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#define REG_AXXX_CP_IB2_BUFSZ 0x0000045b
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#define REG_AXXX_CP_STAT 0x0000047f
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#define AXXX_CP_STAT_CP_BUSY 0x80000000
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#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY 0x40000000
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#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY 0x20000000
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#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY 0x10000000
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#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY 0x08000000
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#define AXXX_CP_STAT_ME_BUSY 0x04000000
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#define AXXX_CP_STAT_MIU_WR_C_BUSY 0x02000000
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#define AXXX_CP_STAT_CP_3D_BUSY 0x00800000
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#define AXXX_CP_STAT_CP_NRT_BUSY 0x00400000
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#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY 0x00200000
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#define AXXX_CP_STAT_RCIU_ME_BUSY 0x00100000
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#define AXXX_CP_STAT_RCIU_PFP_BUSY 0x00080000
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#define AXXX_CP_STAT_MEQ_RING_BUSY 0x00040000
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#define AXXX_CP_STAT_PFP_BUSY 0x00020000
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#define AXXX_CP_STAT_ST_QUEUE_BUSY 0x00010000
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#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY 0x00002000
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#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY 0x00001000
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#define AXXX_CP_STAT_RING_QUEUE_BUSY 0x00000800
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#define AXXX_CP_STAT_CSF_BUSY 0x00000400
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#define AXXX_CP_STAT_CSF_ST_BUSY 0x00000200
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#define AXXX_CP_STAT_EVENT_BUSY 0x00000100
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#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY 0x00000080
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#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY 0x00000040
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#define AXXX_CP_STAT_CSF_RING_BUSY 0x00000020
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#define AXXX_CP_STAT_RCIU_BUSY 0x00000010
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#define AXXX_CP_STAT_RBIU_BUSY 0x00000008
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#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY 0x00000004
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#define AXXX_CP_STAT_MIU_RD_REQ_BUSY 0x00000002
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#define AXXX_CP_STAT_MIU_WR_BUSY 0x00000001
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#define REG_AXXX_CP_SCRATCH_REG0 0x00000578
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#define REG_AXXX_CP_SCRATCH_REG1 0x00000579
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#define REG_AXXX_CP_SCRATCH_REG2 0x0000057a
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#define REG_AXXX_CP_SCRATCH_REG3 0x0000057b
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#define REG_AXXX_CP_SCRATCH_REG4 0x0000057c
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#define REG_AXXX_CP_SCRATCH_REG5 0x0000057d
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#define REG_AXXX_CP_SCRATCH_REG6 0x0000057e
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#define REG_AXXX_CP_SCRATCH_REG7 0x0000057f
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#define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600
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#define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601
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#define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602
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#define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603
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#define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604
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#define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605
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#define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606
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#define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607
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#define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608
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#define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609
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#define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a
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#define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b
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#define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c
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#define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d
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#define REG_AXXX_CP_ME_NRT_DATA 0x0000060e
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#define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612
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#define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613
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#define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614
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#endif /* ADRENO_COMMON_XML */
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