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There's an alternative 5-line mini interrupt controller in the R4k MB ASIC used on the KN04 and KN05 CPU daughtercards. The controller is cascaded from the CPU interrupt input that would be used for the Halt button on the corresponding R3k systems. This change documents the findings so far. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6706/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
86 lines
3.4 KiB
C
86 lines
3.4 KiB
C
/*
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* include/asm-mips/dec/kn05.h
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*
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* DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min
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* or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or
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* KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
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* definitions.
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*
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* Copyright (C) 2002, 2003, 2005, 2008 Maciej W. Rozycki
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* WARNING! All this information is pure guesswork based on the
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* ROM. It is provided here in hope it will give someone some
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* food for thought. No documentation for the KN05 nor the KN04
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* module has been located so far.
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*/
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#ifndef __ASM_MIPS_DEC_KN05_H
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#define __ASM_MIPS_DEC_KN05_H
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#include <asm/dec/ioasic_addrs.h>
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/*
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* The oncard MB (Memory Buffer) ASIC provides an additional address
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* decoder. Certain address ranges within the "high" 16 slots are
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* passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA.
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* Others are handled locally. "Low" slots are always passed.
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*/
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#define KN4K_SLOT_BASE 0x1fc00000
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#define KN4K_MB_ROM (0*IOASIC_SLOT_SIZE) /* KN05/KN04 card ROM */
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#define KN4K_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */
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#define KN4K_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */
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#define KN4K_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */
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#define KN4K_MB_INT (4*IOASIC_SLOT_SIZE) /* MB interrupt register */
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#define KN4K_MB_EA (5*IOASIC_SLOT_SIZE) /* MB error address? */
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#define KN4K_MB_EC (6*IOASIC_SLOT_SIZE) /* MB error ??? */
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#define KN4K_MB_CSR (7*IOASIC_SLOT_SIZE) /* MB control & status */
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#define KN4K_RES_08 (8*IOASIC_SLOT_SIZE) /* unused? */
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#define KN4K_RES_09 (9*IOASIC_SLOT_SIZE) /* unused? */
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#define KN4K_RES_10 (10*IOASIC_SLOT_SIZE) /* unused? */
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#define KN4K_RES_11 (11*IOASIC_SLOT_SIZE) /* unused? */
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#define KN4K_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */
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#define KN4K_RES_13 (13*IOASIC_SLOT_SIZE) /* unused? */
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#define KN4K_RES_14 (14*IOASIC_SLOT_SIZE) /* unused? */
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#define KN4K_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */
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/*
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* MB ASIC interrupt bits.
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*/
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#define KN4K_MB_INR_MB 4 /* ??? */
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#define KN4K_MB_INR_MT 3 /* memory, I/O bus read/write errors */
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#define KN4K_MB_INR_RES_2 2 /* unused */
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#define KN4K_MB_INR_RTC 1 /* RTC */
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#define KN4K_MB_INR_TC 0 /* I/O ASIC cascade */
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/*
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* Bits for the MB interrupt register.
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* The register appears read-only.
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*/
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#define KN4K_MB_INT_IRQ (0x1f<<0) /* CPU Int[4:0] status. */
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#define KN4K_MB_INT_IRQ_N(n) (1<<(n)) /* Individual status bits. */
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/*
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* Bits for the MB control & status register.
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* Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware.
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*/
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#define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */
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#define KN4K_MB_CSR_F (1<<1) /* ??? */
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#define KN4K_MB_CSR_ECC (0xff<<2) /* ??? */
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#define KN4K_MB_CSR_OD (1<<10) /* ??? */
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#define KN4K_MB_CSR_CP (1<<11) /* ??? */
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#define KN4K_MB_CSR_UNC (1<<12) /* ??? */
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#define KN4K_MB_CSR_IM (1<<13) /* ??? */
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#define KN4K_MB_CSR_NC (1<<14) /* ??? */
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#define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */
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#define KN4K_MB_CSR_MSK (0x1f<<16) /* CPU Int[4:0] mask */
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#define KN4K_MB_CSR_MSK_N(n) (1<<((n)+16)) /* Individual mask bits. */
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#define KN4K_MB_CSR_FW (1<<21) /* ??? */
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#define KN4K_MB_CSR_W (1<<31) /* ??? */
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#endif /* __ASM_MIPS_DEC_KN05_H */
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