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5cbdcc2f49
bit MASTER_CTRL_CLK_SEL_DIS could be set before enter suspend clear it after resume to enable pclk(PCIE clock) switch to low frequency(25M) in some circumstances to save power. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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atl1c_ethtool.c | ||
atl1c_hw.c | ||
atl1c_hw.h | ||
atl1c_main.c | ||
atl1c.h | ||
Makefile |