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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a866374aec
Introduce pagefault_{disable,enable}() and use these where previously we did
manual preempt increments/decrements to make the pagefault handler do the
atomic thing.
Currently they still rely on the increased preempt count, but do not rely on
the disabled preemption, this might go away in the future.
(NOTE: the extra barrier() in pagefault_disable might fix some holes on
machines which have too many registers for their own good)
[heiko.carstens@de.ibm.com: s390 fix]
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: Nick Piggin <npiggin@suse.de>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
181 lines
5.2 KiB
C
181 lines
5.2 KiB
C
/* highmem.h: virtual kernel memory mappings for high memory
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*
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* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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* - Derived from include/asm-i386/highmem.h
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*
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* See Documentation/fujitsu/frv/mmu-layout.txt for more information.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_HIGHMEM_H
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#define _ASM_HIGHMEM_H
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#ifdef __KERNEL__
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#include <linux/init.h>
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#include <asm/mem-layout.h>
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#include <asm/spr-regs.h>
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#include <asm/mb-regs.h>
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#define NR_TLB_LINES 64 /* number of lines in the TLB */
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#ifndef __ASSEMBLY__
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#include <linux/interrupt.h>
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#include <asm/kmap_types.h>
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#include <asm/pgtable.h>
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#ifdef CONFIG_DEBUG_HIGHMEM
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#define HIGHMEM_DEBUG 1
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#else
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#define HIGHMEM_DEBUG 0
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#endif
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/* declarations for highmem.c */
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extern unsigned long highstart_pfn, highend_pfn;
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#define kmap_prot PAGE_KERNEL
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#define kmap_pte ______kmap_pte_in_TLB
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extern pte_t *pkmap_page_table;
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#define flush_cache_kmaps() do { } while (0)
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/*
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* Right now we initialize only a single pte table. It can be extended
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* easily, subsequent pte tables have to be allocated in one physical
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* chunk of RAM.
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*/
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#define LAST_PKMAP PTRS_PER_PTE
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#define LAST_PKMAP_MASK (LAST_PKMAP - 1)
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#define PKMAP_NR(virt) ((virt - PKMAP_BASE) >> PAGE_SHIFT)
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#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
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extern void *kmap_high(struct page *page);
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extern void kunmap_high(struct page *page);
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extern void *kmap(struct page *page);
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extern void kunmap(struct page *page);
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extern struct page *kmap_atomic_to_page(void *ptr);
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#endif /* !__ASSEMBLY__ */
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/*
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* The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap
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* gives a more generic (and caching) interface. But kmap_atomic can
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* be used in IRQ contexts, so in some (very limited) cases we need
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* it.
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*/
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#define KMAP_ATOMIC_CACHE_DAMR 8
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#ifndef __ASSEMBLY__
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#define __kmap_atomic_primary(type, paddr, ampr) \
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({ \
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unsigned long damlr, dampr; \
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\
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dampr = paddr | xAMPRx_L | xAMPRx_M | xAMPRx_S | xAMPRx_SS_16Kb | xAMPRx_V; \
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\
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if (type != __KM_CACHE) \
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asm volatile("movgs %0,dampr"#ampr :: "r"(dampr) : "memory"); \
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else \
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asm volatile("movgs %0,iampr"#ampr"\n" \
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"movgs %0,dampr"#ampr"\n" \
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:: "r"(dampr) : "memory" \
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); \
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\
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asm("movsg damlr"#ampr",%0" : "=r"(damlr)); \
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\
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/*printk("DAMR"#ampr": PRIM sl=%d L=%08lx P=%08lx\n", type, damlr, dampr);*/ \
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\
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(void *) damlr; \
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})
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#define __kmap_atomic_secondary(slot, paddr) \
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({ \
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unsigned long damlr = KMAP_ATOMIC_SECONDARY_FRAME + (slot) * PAGE_SIZE; \
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unsigned long dampr = paddr | xAMPRx_L | xAMPRx_M | xAMPRx_S | xAMPRx_SS_16Kb | xAMPRx_V; \
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\
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asm volatile("movgs %0,tplr \n" \
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"movgs %1,tppr \n" \
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"tlbpr %0,gr0,#2,#1" \
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: : "r"(damlr), "r"(dampr) : "memory"); \
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\
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/*printk("TLB: SECN sl=%d L=%08lx P=%08lx\n", slot, damlr, dampr);*/ \
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\
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(void *) damlr; \
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})
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static inline void *kmap_atomic(struct page *page, enum km_type type)
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{
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unsigned long paddr;
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pagefault_disable();
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paddr = page_to_phys(page);
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switch (type) {
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case 0: return __kmap_atomic_primary(0, paddr, 2);
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case 1: return __kmap_atomic_primary(1, paddr, 3);
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case 2: return __kmap_atomic_primary(2, paddr, 4);
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case 3: return __kmap_atomic_primary(3, paddr, 5);
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case 4: return __kmap_atomic_primary(4, paddr, 6);
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case 5: return __kmap_atomic_primary(5, paddr, 7);
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case 6: return __kmap_atomic_primary(6, paddr, 8);
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case 7: return __kmap_atomic_primary(7, paddr, 9);
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case 8: return __kmap_atomic_primary(8, paddr, 10);
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case 9 ... 9 + NR_TLB_LINES - 1:
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return __kmap_atomic_secondary(type - 9, paddr);
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default:
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BUG();
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return NULL;
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}
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}
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#define __kunmap_atomic_primary(type, ampr) \
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do { \
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asm volatile("movgs gr0,dampr"#ampr"\n" ::: "memory"); \
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if (type == __KM_CACHE) \
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asm volatile("movgs gr0,iampr"#ampr"\n" ::: "memory"); \
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} while(0)
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#define __kunmap_atomic_secondary(slot, vaddr) \
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do { \
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asm volatile("tlbpr %0,gr0,#4,#1" : : "r"(vaddr) : "memory"); \
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} while(0)
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static inline void kunmap_atomic(void *kvaddr, enum km_type type)
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{
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switch (type) {
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case 0: __kunmap_atomic_primary(0, 2); break;
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case 1: __kunmap_atomic_primary(1, 3); break;
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case 2: __kunmap_atomic_primary(2, 4); break;
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case 3: __kunmap_atomic_primary(3, 5); break;
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case 4: __kunmap_atomic_primary(4, 6); break;
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case 5: __kunmap_atomic_primary(5, 7); break;
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case 6: __kunmap_atomic_primary(6, 8); break;
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case 7: __kunmap_atomic_primary(7, 9); break;
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case 8: __kunmap_atomic_primary(8, 10); break;
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case 9 ... 9 + NR_TLB_LINES - 1:
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__kunmap_atomic_secondary(type - 9, kvaddr);
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break;
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default:
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BUG();
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}
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pagefault_enable();
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}
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#endif /* !__ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_HIGHMEM_H */
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