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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a4240d3af6
DRA72-EVM now has an upgrade to Rev C with SR2.0 silicon. As part of this change, a few updates were factored in that were software incompatible with previous board in few areas: - We now use DP83867 ethernet phy instead of older DP838865 which fails in certain use cases. - Two Ethernet ports now instead of the single one in rev B. - polarities changed for certain pcf gpios - Due to SoC phy current requirements, VDDA supplies are split between ldo3 and ldo2 (ldo2 was previously unused). NOTE: DSS (VDDA_VIDEO) is still supplied by ldo5, HDMI is now supplied by LDO2 instead of using LDO3. NOTE: It does not make much sense to spin off a new board compatible flag since there is no real benefit for the same. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
74 lines
1.6 KiB
Plaintext
74 lines
1.6 KiB
Plaintext
/*
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* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "dra72-evm-common.dtsi"
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#include <dt-bindings/net/ti-dp83867.h>
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/ {
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model = "TI DRA722 Rev C EVM";
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memory {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
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};
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};
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&tps65917_regulators {
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ldo2_reg: ldo2 {
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/* LDO2_OUT --> VDDA_1V8_PHY2 */
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regulator-name = "ldo2";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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&hdmi {
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vdda-supply = <&ldo2_reg>;
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};
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&pcf_gpio_21 {
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interrupt-parent = <&gpio3>;
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interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
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};
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&mac {
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mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
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<&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */
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<&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */
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dual_emac;
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};
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&cpsw_emac0 {
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phy_id = <&davinci_mdio>, <2>;
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phy-mode = "rgmii-id";
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dual_emac_res_vlan = <1>;
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};
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&cpsw_emac1 {
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phy_id = <&davinci_mdio>, <3>;
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phy-mode = "rgmii-id";
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dual_emac_res_vlan = <2>;
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};
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&davinci_mdio {
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dp83867_0: ethernet-phy@2 {
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reg = <2>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
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};
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dp83867_1: ethernet-phy@3 {
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reg = <3>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
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};
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};
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