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There are 2 version of QSPI-IP, according to which controller registers sets can be big endian or little endian.There are some other minor changes like RX fifo depth etc. The big endian version uses driver compatible "fsl,ls1021a-qspi" and little endian version uses driver compatible "fsl,ls2080a-qspi" Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Han Xu <han.xu@nxp.com> Link: https://lore.kernel.org/r/1565691791-26167-1-git-send-email-Ashish.Kumar@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
67 lines
1.9 KiB
Plaintext
67 lines
1.9 KiB
Plaintext
* Freescale Quad Serial Peripheral Interface(QuadSPI)
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Required properties:
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- compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
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"fsl,imx7d-qspi", "fsl,imx6ul-qspi",
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"fsl,ls1021a-qspi", "fsl,ls2080a-qspi"
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or
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"fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
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- reg : the first contains the register location and length,
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the second contains the memory mapping address and length
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- reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
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- interrupts : Should contain the interrupt for the device
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- clocks : The clocks needed by the QuadSPI controller
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- clock-names : Should contain the name of the clocks: "qspi_en" and "qspi".
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Required SPI slave node properties:
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- reg: There are two buses (A and B) with two chip selects each.
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This encodes to which bus and CS the flash is connected:
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<0>: Bus A, CS 0
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<1>: Bus A, CS 1
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<2>: Bus B, CS 0
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<3>: Bus B, CS 1
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Example:
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qspi0: quadspi@40044000 {
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compatible = "fsl,vf610-qspi";
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reg = <0x40044000 0x1000>, <0x20000000 0x10000000>;
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reg-names = "QuadSPI", "QuadSPI-memory";
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interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks VF610_CLK_QSPI0_EN>,
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<&clks VF610_CLK_QSPI0>;
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clock-names = "qspi_en", "qspi";
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flash0: s25fl128s@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spansion,s25fl128s", "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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reg = <0>;
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};
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};
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Example showing the usage of two SPI NOR devices on bus A:
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&qspi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi2>;
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status = "okay";
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flash0: n25q256a@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q256a", "jedec,spi-nor";
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spi-max-frequency = <29000000>;
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reg = <0>;
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};
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flash1: n25q256a@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q256a", "jedec,spi-nor";
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spi-max-frequency = <29000000>;
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reg = <1>;
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};
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};
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