mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 09:55:29 +07:00
52fa1927e9
This reverts commit 1b6d7f8742.
This patch would conflict with Dan Williams' "tree-wide convert to
memremap()" series (ioremap_cache replaced by arch_memremap)
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
217 lines
6.9 KiB
C
217 lines
6.9 KiB
C
/*
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* Based on arch/arm/include/asm/io.h
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*
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* Copyright (C) 1996-2000 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_IO_H
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#define __ASM_IO_H
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#ifdef __KERNEL__
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#include <linux/types.h>
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#include <linux/blk_types.h>
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#include <asm/byteorder.h>
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#include <asm/barrier.h>
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#include <asm/memory.h>
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#include <asm/pgtable.h>
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#include <asm/early_ioremap.h>
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#include <asm/alternative.h>
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#include <asm/cpufeature.h>
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#include <xen/xen.h>
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/*
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* Generic IO read/write. These perform native-endian accesses.
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*/
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#define __raw_writeb __raw_writeb
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static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
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{
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asm volatile("strb %w0, [%1]" : : "r" (val), "r" (addr));
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}
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#define __raw_writew __raw_writew
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static inline void __raw_writew(u16 val, volatile void __iomem *addr)
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{
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asm volatile("strh %w0, [%1]" : : "r" (val), "r" (addr));
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}
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#define __raw_writel __raw_writel
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static inline void __raw_writel(u32 val, volatile void __iomem *addr)
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{
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asm volatile("str %w0, [%1]" : : "r" (val), "r" (addr));
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}
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#define __raw_writeq __raw_writeq
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static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
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{
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asm volatile("str %0, [%1]" : : "r" (val), "r" (addr));
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}
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#define __raw_readb __raw_readb
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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u8 val;
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asm volatile(ALTERNATIVE("ldrb %w0, [%1]",
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"ldarb %w0, [%1]",
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ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
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: "=r" (val) : "r" (addr));
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return val;
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}
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#define __raw_readw __raw_readw
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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u16 val;
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asm volatile(ALTERNATIVE("ldrh %w0, [%1]",
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"ldarh %w0, [%1]",
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ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
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: "=r" (val) : "r" (addr));
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return val;
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}
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#define __raw_readl __raw_readl
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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u32 val;
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asm volatile(ALTERNATIVE("ldr %w0, [%1]",
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"ldar %w0, [%1]",
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ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
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: "=r" (val) : "r" (addr));
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return val;
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}
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#define __raw_readq __raw_readq
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static inline u64 __raw_readq(const volatile void __iomem *addr)
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{
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u64 val;
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asm volatile(ALTERNATIVE("ldr %0, [%1]",
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"ldar %0, [%1]",
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ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
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: "=r" (val) : "r" (addr));
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return val;
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}
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/* IO barriers */
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#define __iormb() rmb()
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#define __iowmb() wmb()
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#define mmiowb() do { } while (0)
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/*
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* Relaxed I/O memory access primitives. These follow the Device memory
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* ordering rules but do not guarantee any ordering relative to Normal memory
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* accesses.
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*/
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#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
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#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
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#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
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#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
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#define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c)))
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#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
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#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
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#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
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/*
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* I/O memory access primitives. Reads are ordered relative to any
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* following Normal memory access. Writes are ordered relative to any prior
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* Normal memory access.
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*/
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#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
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#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
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#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
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#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
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#define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); })
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#define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); })
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#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); })
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#define writeq(v,c) ({ __iowmb(); writeq_relaxed((v),(c)); })
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/*
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* I/O port access primitives.
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*/
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#define arch_has_dev_port() (1)
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#define IO_SPACE_LIMIT (PCI_IO_SIZE - 1)
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#define PCI_IOBASE ((void __iomem *)PCI_IO_START)
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/*
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* String version of I/O memory access operations.
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*/
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extern void __memcpy_fromio(void *, const volatile void __iomem *, size_t);
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extern void __memcpy_toio(volatile void __iomem *, const void *, size_t);
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extern void __memset_io(volatile void __iomem *, int, size_t);
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#define memset_io(c,v,l) __memset_io((c),(v),(l))
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#define memcpy_fromio(a,c,l) __memcpy_fromio((a),(c),(l))
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#define memcpy_toio(c,a,l) __memcpy_toio((c),(a),(l))
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/*
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* I/O memory mapping functions.
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*/
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extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot);
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extern void __iounmap(volatile void __iomem *addr);
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extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size);
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#define ioremap(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
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#define ioremap_nocache(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
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#define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
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#define ioremap_wt(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
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#define iounmap __iounmap
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/*
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* io{read,write}{16,32}be() macros
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*/
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#define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
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#define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
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#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
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#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem
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* access
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*/
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#define xlate_dev_mem_ptr(p) __va(p)
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/*
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* Convert a virtual cached pointer to an uncached pointer
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*/
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#define xlate_dev_kmem_ptr(p) p
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#include <asm-generic/io.h>
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/*
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* More restrictive address range checking than the default implementation
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* (PHYS_OFFSET and PHYS_MASK taken into account).
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*/
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#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
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extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
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extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
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extern int devmem_is_allowed(unsigned long pfn);
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struct bio_vec;
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extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
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const struct bio_vec *vec2);
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#define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \
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(__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \
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(!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))
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#endif /* __KERNEL__ */
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#endif /* __ASM_IO_H */
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