mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 17:51:21 +07:00
ffc7bb3857
Added support for the bar descriptor. This type is used for FPGAs connect to the LPC or to a non PCI bus. The Bar descriptor could have a maximum of 6 BARs. Each of the devices within the FPGA could be mapped to a different BAR. The BAR descriptor is comparable to the PCI header. Signed-off-by: Andreas Werner <andreas.werner@men.de> [ free bar descriptor in the non-error case ] Signed-off-by: Johannes Thumshirn <jthumshirn@suse.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
254 lines
5.1 KiB
C
254 lines
5.1 KiB
C
#include <linux/types.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/io.h>
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#include <linux/mcb.h>
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#include "mcb-internal.h"
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struct mcb_parse_priv {
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phys_addr_t mapbase;
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void __iomem *base;
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};
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#define for_each_chameleon_cell(dtype, p) \
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for ((dtype) = get_next_dtype((p)); \
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(dtype) != CHAMELEON_DTYPE_END; \
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(dtype) = get_next_dtype((p)))
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static inline uint32_t get_next_dtype(void __iomem *p)
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{
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uint32_t dtype;
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dtype = readl(p);
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return dtype >> 28;
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}
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static int chameleon_parse_bdd(struct mcb_bus *bus,
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struct chameleon_bar *cb,
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void __iomem *base)
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{
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return 0;
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}
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static int chameleon_parse_gdd(struct mcb_bus *bus,
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struct chameleon_bar *cb,
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void __iomem *base, int bar_count)
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{
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struct chameleon_gdd __iomem *gdd =
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(struct chameleon_gdd __iomem *) base;
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struct mcb_device *mdev;
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u32 dev_mapbase;
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u32 offset;
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u32 size;
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int ret;
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__le32 reg1;
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__le32 reg2;
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mdev = mcb_alloc_dev(bus);
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if (!mdev)
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return -ENOMEM;
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reg1 = readl(&gdd->reg1);
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reg2 = readl(&gdd->reg2);
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offset = readl(&gdd->offset);
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size = readl(&gdd->size);
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mdev->id = GDD_DEV(reg1);
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mdev->rev = GDD_REV(reg1);
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mdev->var = GDD_VAR(reg1);
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mdev->bar = GDD_BAR(reg2);
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mdev->group = GDD_GRP(reg2);
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mdev->inst = GDD_INS(reg2);
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/*
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* If the BAR is missing, dev_mapbase is zero, or if the
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* device is IO mapped we just print a warning and go on with the
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* next device, instead of completely stop the gdd parser
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*/
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if (mdev->bar > bar_count - 1) {
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pr_info("No BAR for 16z%03d\n", mdev->id);
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ret = 0;
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goto err;
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}
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dev_mapbase = cb[mdev->bar].addr;
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if (!dev_mapbase) {
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pr_info("BAR not assigned for 16z%03d\n", mdev->id);
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ret = 0;
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goto err;
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}
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if (dev_mapbase & 0x01) {
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pr_info("IO mapped Device (16z%03d) not yet supported\n",
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mdev->id);
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ret = 0;
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goto err;
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}
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pr_debug("Found a 16z%03d\n", mdev->id);
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mdev->irq.start = GDD_IRQ(reg1);
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mdev->irq.end = GDD_IRQ(reg1);
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mdev->irq.flags = IORESOURCE_IRQ;
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mdev->mem.start = dev_mapbase + offset;
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mdev->mem.end = mdev->mem.start + size - 1;
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mdev->mem.flags = IORESOURCE_MEM;
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mdev->is_added = false;
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ret = mcb_device_register(bus, mdev);
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if (ret < 0)
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goto err;
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return 0;
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err:
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mcb_free_dev(mdev);
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return ret;
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}
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static void chameleon_parse_bar(void __iomem *base,
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struct chameleon_bar *cb, int bar_count)
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{
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char __iomem *p = base;
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int i;
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/* skip reg1 */
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p += sizeof(__le32);
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for (i = 0; i < bar_count; i++) {
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cb[i].addr = readl(p);
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cb[i].size = readl(p + 4);
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p += sizeof(struct chameleon_bar);
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}
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}
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static int chameleon_get_bar(char __iomem **base, phys_addr_t mapbase,
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struct chameleon_bar **cb)
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{
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struct chameleon_bar *c;
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int bar_count;
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__le32 reg;
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u32 dtype;
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/*
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* For those devices which are not connected
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* to the PCI Bus (e.g. LPC) there is a bar
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* descriptor located directly after the
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* chameleon header. This header is comparable
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* to a PCI header.
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*/
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dtype = get_next_dtype(*base);
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if (dtype == CHAMELEON_DTYPE_BAR) {
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reg = readl(*base);
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bar_count = BAR_CNT(reg);
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if (bar_count <= 0 && bar_count > CHAMELEON_BAR_MAX)
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return -ENODEV;
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c = kcalloc(bar_count, sizeof(struct chameleon_bar),
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GFP_KERNEL);
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if (!c)
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return -ENOMEM;
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chameleon_parse_bar(*base, c, bar_count);
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*base += BAR_DESC_SIZE(bar_count);
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} else {
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c = kzalloc(sizeof(struct chameleon_bar), GFP_KERNEL);
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if (!c)
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return -ENOMEM;
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bar_count = 1;
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c->addr = mapbase;
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}
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*cb = c;
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return bar_count;
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}
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int chameleon_parse_cells(struct mcb_bus *bus, phys_addr_t mapbase,
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void __iomem *base)
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{
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struct chameleon_fpga_header *header;
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struct chameleon_bar *cb;
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char __iomem *p = base;
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int num_cells = 0;
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uint32_t dtype;
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int bar_count;
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int ret = 0;
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u32 hsize;
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hsize = sizeof(struct chameleon_fpga_header);
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header = kzalloc(hsize, GFP_KERNEL);
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if (!header)
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return -ENOMEM;
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/* Extract header information */
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memcpy_fromio(header, p, hsize);
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/* We only support chameleon v2 at the moment */
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header->magic = le16_to_cpu(header->magic);
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if (header->magic != CHAMELEONV2_MAGIC) {
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pr_err("Unsupported chameleon version 0x%x\n",
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header->magic);
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ret = -ENODEV;
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goto free_header;
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}
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p += hsize;
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bus->revision = header->revision;
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bus->model = header->model;
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bus->minor = header->minor;
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snprintf(bus->name, CHAMELEON_FILENAME_LEN + 1, "%s",
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header->filename);
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bar_count = chameleon_get_bar(&p, mapbase, &cb);
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if (bar_count < 0)
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goto free_header;
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for_each_chameleon_cell(dtype, p) {
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switch (dtype) {
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case CHAMELEON_DTYPE_GENERAL:
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ret = chameleon_parse_gdd(bus, cb, p, bar_count);
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if (ret < 0)
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goto free_bar;
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p += sizeof(struct chameleon_gdd);
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break;
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case CHAMELEON_DTYPE_BRIDGE:
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chameleon_parse_bdd(bus, cb, p);
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p += sizeof(struct chameleon_bdd);
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break;
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case CHAMELEON_DTYPE_END:
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break;
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default:
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pr_err("Invalid chameleon descriptor type 0x%x\n",
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dtype);
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ret = -EINVAL;
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goto free_bar;
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}
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num_cells++;
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}
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if (num_cells == 0)
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num_cells = -EINVAL;
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kfree(cb);
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kfree(header);
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return num_cells;
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free_bar:
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kfree(cb);
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free_header:
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kfree(header);
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return ret;
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}
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EXPORT_SYMBOL_GPL(chameleon_parse_cells);
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