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4e7e8017a8
Add support to configure multiple pins in each register, existing
implementation added by [1] does not support full fledge multiple pin
configuration in single register, reports a pin clash when different
modules configure different bits of same register. The issue reported
and discussed here
http://www.spinics.net/lists/arm-kernel/msg235213.html
With pinctrl-single,bits-per-mux property specified, use function-mask
property to find out number pins to configure. Allocate and register
pin control functions based sub mask.
Tested on da850/omap-l138 EVM.
does not support variable submask for pins.
does not support pinconf.
[1] "pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux"
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| .. | ||
| allwinner,sunxi-pinctrl.txt | ||
| atmel,at91-pinctrl.txt | ||
| brcm,bcm2835-gpio.txt | ||
| fsl,imx6dl-pinctrl.txt | ||
| fsl,imx6q-pinctrl.txt | ||
| fsl,imx6sl-pinctrl.txt | ||
| fsl,imx35-pinctrl.txt | ||
| fsl,imx51-pinctrl.txt | ||
| fsl,imx53-pinctrl.txt | ||
| fsl,imx-pinctrl.txt | ||
| fsl,mxs-pinctrl.txt | ||
| fsl,vf610-pinctrl.txt | ||
| lantiq,falcon-pinumx.txt | ||
| lantiq,xway-pinumx.txt | ||
| marvell,armada-370-pinctrl.txt | ||
| marvell,armada-xp-pinctrl.txt | ||
| marvell,dove-pinctrl.txt | ||
| marvell,kirkwood-pinctrl.txt | ||
| marvell,mvebu-pinctrl.txt | ||
| nvidia,tegra20-pinmux.txt | ||
| nvidia,tegra30-pinmux.txt | ||
| nvidia,tegra114-pinmux.txt | ||
| pinctrl_spear.txt | ||
| pinctrl-bindings.txt | ||
| pinctrl-single.txt | ||
| pinctrl-sirf.txt | ||
| pinctrl-vt8500.txt | ||
| samsung-pinctrl.txt | ||
| ste,nomadik.txt | ||